Lines Matching +full:1 +full:- +full:7
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
22 "BriefDescription": "Speculative and retired macro-conditional branches.",
23 "Counter": "0,1,2,3",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
31 …"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indi…
32 "Counter": "0,1,2,3",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
50 "Counter": "0,1,2,3",
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
67 "BriefDescription": "Not taken macro-conditional branches.",
68 "Counter": "0,1,2,3",
69 "CounterHTOff": "0,1,2,3,4,5,6,7",
76 "BriefDescription": "Taken speculative and retired macro-conditional branches.",
77 "Counter": "0,1,2,3",
78 "CounterHTOff": "0,1,2,3,4,5,6,7",
85 …"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding…
86 "Counter": "0,1,2,3",
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
104 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
113 "Counter": "0,1,2,3",
114 "CounterHTOff": "0,1,2,3,4,5,6,7",
122 "Counter": "0,1,2,3",
123 "CounterHTOff": "0,1,2,3,4,5,6,7",
131 "Counter": "0,1,2,3",
132 "CounterHTOff": "0,1,2,3,4,5,6,7",
140 "Counter": "0,1,2,3",
141 "CounterHTOff": "0,1,2,3",
150 "Counter": "0,1,2,3",
151 "CounterHTOff": "0,1,2,3,4,5,6,7",
154 "PEBS": "1",
161 "Counter": "0,1,2,3",
162 "CounterHTOff": "0,1,2,3,4,5,6,7",
171 "Counter": "0,1,2,3",
172 "CounterHTOff": "0,1,2,3,4,5,6,7",
175 "PEBS": "1",
181 "Counter": "0,1,2,3",
182 "CounterHTOff": "0,1,2,3,4,5,6,7",
185 "PEBS": "1",
191 "Counter": "0,1,2,3",
192 "CounterHTOff": "0,1,2,3,4,5,6,7",
195 "PEBS": "1",
202 "Counter": "0,1,2,3",
203 "CounterHTOff": "0,1,2,3,4,5,6,7",
206 "PEBS": "1",
213 "Counter": "0,1,2,3",
214 "CounterHTOff": "0,1,2,3,4,5,6,7",
223 "Counter": "0,1,2,3",
224 "CounterHTOff": "0,1,2,3,4,5,6,7",
233 "Counter": "0,1,2,3",
234 "CounterHTOff": "0,1,2,3,4,5,6,7",
242 "Counter": "0,1,2,3",
243 "CounterHTOff": "0,1,2,3,4,5,6,7",
251 "Counter": "0,1,2,3",
252 "CounterHTOff": "0,1,2,3,4,5,6,7",
260 "Counter": "0,1,2,3",
261 "CounterHTOff": "0,1,2,3,4,5,6,7",
269 "Counter": "0,1,2,3",
270 "CounterHTOff": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
279 "CounterHTOff": "0,1,2,3,4,5,6,7",
287 "Counter": "0,1,2,3",
288 "CounterHTOff": "0,1,2,3,4,5,6,7",
296 "Counter": "0,1,2,3",
297 "CounterHTOff": "0,1,2,3,4,5,6,7",
305 "Counter": "0,1,2,3",
306 "CounterHTOff": "0,1,2,3",
316 "Counter": "0,1,2,3",
317 "CounterHTOff": "0,1,2,3,4,5,6,7",
320 "PEBS": "1",
326 "Counter": "0,1,2,3",
327 "CounterHTOff": "0,1,2,3,4,5,6,7",
330 "PEBS": "1",
337 "Counter": "0,1,2,3",
338 "CounterHTOff": "0,1,2,3",
346 "Counter": "0,1,2,3",
347 "CounterHTOff": "0,1,2,3,4,5,6,7",
355 "AnyThread": "1",
357 "Counter": "0,1,2,3",
358 "CounterHTOff": "0,1,2,3,4,5,6,7",
367 "Counter": "0,1,2,3",
368 "CounterHTOff": "0,1,2,3,4,5,6,7",
385 "Counter": "0,1,2,3",
386 "CounterHTOff": "0,1,2,3,4,5,6,7",
394 "AnyThread": "1",
396 "Counter": "0,1,2,3",
397 "CounterHTOff": "0,1,2,3,4,5,6,7",
406 "Counter": "Fixed counter 1",
407 "CounterHTOff": "Fixed counter 1",
414 "AnyThread": "1",
416 "Counter": "Fixed counter 1",
417 "CounterHTOff": "Fixed counter 1",
424 "Counter": "0,1,2,3",
425 "CounterHTOff": "0,1,2,3,4,5,6,7",
432 "AnyThread": "1",
434 "Counter": "0,1,2,3",
435 "CounterHTOff": "0,1,2,3,4,5,6,7",
453 "Counter": "0,1,2,3",
454 "CounterHTOff": "0,1,2,3,4,5,6,7",
455 "CounterMask": "1",
465 "Counter": "0,1,2,3",
466 "CounterHTOff": "0,1,2,3",
475 …"BriefDescription": "This event increments by 1 for every cycle where there was no execute for thi…
476 "Counter": "0,1,2,3",
477 "CounterHTOff": "0,1,2,3",
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3",
510 "Counter": "0,1,2,3",
511 "CounterHTOff": "0,1,2,3",
521 "Counter": "0,1,2,3",
522 "CounterHTOff": "0,1,2,3,4,5,6,7",
531 "Counter": "0,1,2,3",
532 "CounterHTOff": "0,1,2,3,4,5,6,7",
545 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
550 … "BriefDescription": "Number of instructions retired. General Counter - architectural event",
551 "Counter": "0,1,2,3",
552 "CounterHTOff": "0,1,2,3,4,5,6,7",
561 "Counter": "1",
562 "CounterHTOff": "1",
573 "Counter": "0,1,2,3",
574 "CounterHTOff": "0,1,2,3,4,5,6,7",
577 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
583 "Counter": "0,1,2,3",
584 "CounterHTOff": "0,1,2,3,4,5,6,7",
585 "CounterMask": "1",
593 "AnyThread": "1",
595 "Counter": "0,1,2,3",
596 "CounterHTOff": "0,1,2,3,4,5,6,7",
597 "CounterMask": "1",
606 "Counter": "0,1,2,3",
607 "CounterHTOff": "0,1,2,3,4,5,6,7",
616 "Counter": "0,1,2,3",
617 "CounterHTOff": "0,1,2,3,4,5,6,7",
626 "Counter": "0,1,2,3",
627 "CounterHTOff": "0,1,2,3,4,5,6,7",
635 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware pref…
636 "Counter": "0,1,2,3",
637 "CounterHTOff": "0,1,2,3,4,5,6,7",
640 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefe…
645 …"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software pref…
646 "Counter": "0,1,2,3",
647 "CounterHTOff": "0,1,2,3,4,5,6,7",
650 …"PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefe…
656 "Counter": "0,1,2,3",
657 "CounterHTOff": "0,1,2,3,4,5,6,7",
666 "Counter": "0,1,2,3",
667 "CounterHTOff": "0,1,2,3,4,5,6,7",
668 "CounterMask": "1",
676 "Counter": "0,1,2,3",
677 "CounterHTOff": "0,1,2,3,4,5,6,7",
686 "Counter": "0,1,2,3",
687 "CounterHTOff": "0,1,2,3,4,5,6,7",
688 "CounterMask": "1",
689 "EdgeDetect": "1",
696 …"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nuke…
697 "Counter": "0,1,2,3",
698 "CounterHTOff": "0,1,2,3,4,5,6,7",
706 "Counter": "0,1,2,3",
707 "CounterHTOff": "0,1,2,3,4,5,6,7",
714 "BriefDescription": "Self-modifying code (SMC) detected.",
715 "Counter": "0,1,2,3",
716 "CounterHTOff": "0,1,2,3,4,5,6,7",
719 …"PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which …
725 "Counter": "0,1,2,3",
726 "CounterHTOff": "0,1,2,3,4,5,6,7",
735 "Counter": "0,1,2,3",
736 "CounterHTOff": "0,1,2,3,4,5,6,7",
745 "Counter": "0,1,2,3",
746 "CounterHTOff": "0,1,2,3,4,5,6,7",
754 "BriefDescription": "Resource-related stall cycles",
755 "Counter": "0,1,2,3",
756 "CounterHTOff": "0,1,2,3,4,5,6,7",
765 "BriefDescription": "Cycles stalled due to re-order buffer full.",
766 "Counter": "0,1,2,3",
767 "CounterHTOff": "0,1,2,3,4,5,6,7",
775 "Counter": "0,1,2,3",
776 "CounterHTOff": "0,1,2,3,4,5,6,7",
784 "Counter": "0,1,2,3",
785 "CounterHTOff": "0,1,2,3,4,5,6,7",
794 "Counter": "0,1,2,3",
795 "CounterHTOff": "0,1,2,3,4,5,6,7",
804 "Counter": "0,1,2,3",
805 "CounterHTOff": "0,1,2,3,4,5,6,7",
808 …micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an u…
814 "Counter": "0,1,2,3",
815 "CounterHTOff": "0,1,2,3,4,5,6,7",
816 "CounterMask": "1",
817 "EdgeDetect": "1",
820 "Invert": "1",
826 "Counter": "0,1,2,3",
827 "CounterHTOff": "0,1,2,3,4,5,6,7",
834 "BriefDescription": "Cycles per thread when uops are executed in port 1.",
835 "Counter": "0,1,2,3",
836 "CounterHTOff": "0,1,2,3,4,5,6,7",
844 "Counter": "0,1,2,3",
845 "CounterHTOff": "0,1,2,3,4,5,6,7",
853 "Counter": "0,1,2,3",
854 "CounterHTOff": "0,1,2,3,4,5,6,7",
862 "Counter": "0,1,2,3",
863 "CounterHTOff": "0,1,2,3,4,5,6,7",
871 "Counter": "0,1,2,3",
872 "CounterHTOff": "0,1,2,3,4,5,6,7",
880 "Counter": "0,1,2,3",
881 "CounterHTOff": "0,1,2,3,4,5,6,7",
888 "BriefDescription": "Cycles per thread when uops are executed in port 7.",
889 "Counter": "0,1,2,3",
890 "CounterHTOff": "0,1,2,3,4,5,6,7",
898 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7",
903 "PublicDescription": "Counts total number of uops to be executed per-core each cycle.",
908 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
909 "Counter": "0,1,2,3",
910 "CounterHTOff": "0,1,2,3,4,5,6,7",
911 "CounterMask": "1",
919 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
920 "Counter": "0,1,2,3",
921 "CounterHTOff": "0,1,2,3,4,5,6,7",
930 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
931 "Counter": "0,1,2,3",
932 "CounterHTOff": "0,1,2,3,4,5,6,7",
941 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
942 "Counter": "0,1,2,3",
943 "CounterHTOff": "0,1,2,3,4,5,6,7",
952 "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
953 "Counter": "0,1,2,3",
954 "CounterHTOff": "0,1,2,3,4,5,6,7",
958 "Invert": "1",
963 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
964 "Counter": "0,1,2,3",
965 "CounterHTOff": "0,1,2,3",
966 "CounterMask": "1",
975 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
976 "Counter": "0,1,2,3",
977 "CounterHTOff": "0,1,2,3",
987 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
988 "Counter": "0,1,2,3",
989 "CounterHTOff": "0,1,2,3",
999 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
1000 "Counter": "0,1,2,3",
1001 "CounterHTOff": "0,1,2,3",
1011 "Counter": "0,1,2,3",
1012 "CounterHTOff": "0,1,2,3",
1013 "CounterMask": "1",
1017 "Invert": "1",
1023 "Counter": "0,1,2,3",
1024 "CounterHTOff": "0,1,2,3,4,5,6,7",
1032 "AnyThread": "1",
1034 "Counter": "0,1,2,3",
1035 "CounterHTOff": "0,1,2,3,4,5,6,7",
1042 "BriefDescription": "Cycles per thread when uops are executed in port 1",
1043 "Counter": "0,1,2,3",
1044 "CounterHTOff": "0,1,2,3,4,5,6,7",
1047 "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.",
1052 "AnyThread": "1",
1053 "BriefDescription": "Cycles per core when uops are executed in port 1.",
1054 "Counter": "0,1,2,3",
1055 "CounterHTOff": "0,1,2,3,4,5,6,7",
1063 "Counter": "0,1,2,3",
1064 "CounterHTOff": "0,1,2,3,4,5,6,7",
1072 "AnyThread": "1",
1074 "Counter": "0,1,2,3",
1075 "CounterHTOff": "0,1,2,3,4,5,6,7",
1083 "Counter": "0,1,2,3",
1084 "CounterHTOff": "0,1,2,3,4,5,6,7",
1092 "AnyThread": "1",
1094 "Counter": "0,1,2,3",
1095 "CounterHTOff": "0,1,2,3,4,5,6,7",
1103 "Counter": "0,1,2,3",
1104 "CounterHTOff": "0,1,2,3,4,5,6,7",
1112 "AnyThread": "1",
1114 "Counter": "0,1,2,3",
1115 "CounterHTOff": "0,1,2,3,4,5,6,7",
1123 "Counter": "0,1,2,3",
1124 "CounterHTOff": "0,1,2,3,4,5,6,7",
1132 "AnyThread": "1",
1134 "Counter": "0,1,2,3",
1135 "CounterHTOff": "0,1,2,3,4,5,6,7",
1143 "Counter": "0,1,2,3",
1144 "CounterHTOff": "0,1,2,3,4,5,6,7",
1152 "AnyThread": "1",
1154 "Counter": "0,1,2,3",
1155 "CounterHTOff": "0,1,2,3,4,5,6,7",
1162 "BriefDescription": "Cycles per thread when uops are executed in port 7",
1163 "Counter": "0,1,2,3",
1164 "CounterHTOff": "0,1,2,3,4,5,6,7",
1167 "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.",
1172 "AnyThread": "1",
1173 "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
1174 "Counter": "0,1,2,3",
1175 "CounterHTOff": "0,1,2,3,4,5,6,7",
1183 "Counter": "0,1,2,3",
1184 "CounterHTOff": "0,1,2,3,4,5,6,7",
1187 …ued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stag…
1192 "AnyThread": "1",
1194 "Counter": "0,1,2,3",
1195 "CounterHTOff": "0,1,2,3",
1196 "CounterMask": "1",
1199 "Invert": "1",
1204 …"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensiti…
1205 "Counter": "0,1,2,3",
1206 "CounterHTOff": "0,1,2,3,4,5,6,7",
1209 "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.",
1215 "Counter": "0,1,2,3",
1216 "CounterHTOff": "0,1,2,3,4,5,6,7",
1225 "Counter": "0,1,2,3",
1226 "CounterHTOff": "0,1,2,3,4,5,6,7",
1235 "Counter": "0,1,2,3",
1236 "CounterHTOff": "0,1,2,3",
1237 "CounterMask": "1",
1240 "Invert": "1",
1246 "Counter": "0,1,2,3",
1247 "CounterHTOff": "0,1,2,3,4,5,6,7",
1250 "PEBS": "1",
1251 …"PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count acti…
1256 "AnyThread": "1",
1258 "Counter": "0,1,2,3",
1259 "CounterHTOff": "0,1,2,3",
1260 "CounterMask": "1",
1263 "Invert": "1",
1269 "Counter": "0,1,2,3",
1270 "CounterHTOff": "0,1,2,3,4,5,6,7",
1273 "PEBS": "1",
1274 …used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4…
1280 "Counter": "0,1,2,3",
1281 "CounterHTOff": "0,1,2,3",
1282 "CounterMask": "1",
1285 "Invert": "1",
1291 "Counter": "0,1,2,3",
1292 "CounterHTOff": "0,1,2,3",
1296 "Invert": "1",