Lines Matching +full:3 +full:- +full:line
5 "Counter": "0,1,2,3",
9 "PEBScounters": "0,1,2,3",
17 "Counter": "0,1,2,3",
21 "PEBScounters": "0,1,2,3",
29 "Counter": "0,1,2,3",
33 "PEBScounters": "0,1,2,3",
41 "Counter": "0,1,2,3",
45 "PEBScounters": "0,1,2,3",
51 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo…
53 "Counter": "0,1,2,3",
57 "PEBScounters": "0,1,2,3",
58 …Line. The event strives to count on a cache line basis, so that multiple fetches to a single cach…
63 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
65 "Counter": "0,1,2,3",
69 "PEBScounters": "0,1,2,3",
70 …Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis…
75 …"BriefDescription": "References per ICache line that are not available in the ICache (miss). This …
77 "Counter": "0,1,2,3",
81 "PEBScounters": "0,1,2,3",
82 …Line and that cache line is not in the ICache (miss). The event strives to count on a cache line …
89 "Counter": "0,1,2,3",
93 "PEBScounters": "0,1,2,3",
94 … read from the MSROM. The most common case that this counts is when a micro-coded instruction is …