Lines Matching full:requires
255 …"BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplica…
276 …d & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
291 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE…
306 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
321 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
336 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
351 …2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
366 … "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[…
381 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
396 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
411 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
426 …d & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
441 …read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[…
456 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
471 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
486 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
501 …ore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
516 …"PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCO…
531 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
546 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
561 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
576 …d & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
591 …eads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[…
606 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
621 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
636 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
651 …lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
666 …"PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCO…
681 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
696 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
711 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
726 …che evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
741 …eback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[…
756 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
771 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
786 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
801 …ruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
816 …ide prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[…
831 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
846 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
861 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
876 …l cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
891 …ounts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[…
906 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
921 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
936 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
951 …ta cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
966 …requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[…
981 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
996 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1011 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1026 …mporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1041 …memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1056 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1071 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1086 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1101 …he prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1116 … reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1131 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1146 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1161 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1176 …he prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1191 …eline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1206 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1221 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1236 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1251 …L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1266 …r ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1281 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1296 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1311 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1326 …emory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1341 … to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1356 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1371 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1386 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…
1401 … instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[…
1416 …ache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[…
1431 …a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[…
1446 …miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[…
1461 …r cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[…