Lines Matching +full:3 +full:- +full:line
5 "Counter": "0,1,2,3",
15 "Counter": "0,1,2,3",
25 "Counter": "0,1,2,3",
35 "Counter": "0,1,2,3",
43 …"BriefDescription": "References per ICache line. This event counts differently than Intel processo…
45 "Counter": "0,1,2,3",
48 …Line. The event strives to count on a cache line basis, so that multiple fetches to a single cach…
53 …"BriefDescription": "References per ICache line that are available in the ICache (hit). This event…
55 "Counter": "0,1,2,3",
58 …Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis…
63 …"BriefDescription": "References per ICache line that are not available in the ICache (miss). This …
65 "Counter": "0,1,2,3",
68 …Line and that cache line is not in the ICache (miss). The event strives to count on a cache line …
75 "Counter": "0,1,2,3",
78 … read from the MSROM. The most common case that this counts is when a micro-coded instruction is …