Lines Matching +full:front +full:- +full:end

3 …front end is resteered, mainly when the BPU cannot provide a correct prediction and this is correc…
8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
13         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23         "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
101         "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
109 …ter an interval where the front-end delivered no uops for a period of at least 1 cycle which was n…
115 … after an interval where the front-end delivered no uops for a period of 128 cycles which was not …
128 …d after an interval where the front-end delivered no uops for a period of 16 cycles which was not …
136 …ons that are delivered to the back-end after a front-end stall of at least 16 cycles. During this …
142 …d after an interval where the front-end delivered no uops for a period of 2 cycles which was not i…
155 … after an interval where the front-end delivered no uops for a period of 256 cycles which was not …
168 …ter an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was …
176 …delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles.…
182 …er an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was …
195 …er an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was …
208 …d after an interval where the front-end delivered no uops for a period of 32 cycles which was not …
216 …ons that are delivered to the back-end after a front-end stall of at least 32 cycles. During this …
222 …d after an interval where the front-end delivered no uops for a period of 4 cycles which was not i…
235 … after an interval where the front-end delivered no uops for a period of 512 cycles which was not …
248 …d after an interval where the front-end delivered no uops for a period of 64 cycles which was not …
261 …d after an interval where the front-end delivered no uops for a period of 8 cycles which was not i…
269 …ions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this …
299 …etch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
308 …tch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity…
471 …) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation T…
482 …"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resour…
504 …"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to…
509         "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
515         "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.",
520         "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
526         "PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",