Lines Matching +full:per +full:- +full:cpu
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
11 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
15 …etric represents fraction of slots the CPU was stalled due to Frontend latency issues. For exampl…
19 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruct…
23 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruc…
27 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruct…
28 …"MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_…
31 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruc…
35 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
39 …CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching o…
43 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
47 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch …
51 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
55 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch …
59 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new bran…
60 "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
63 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new bra…
67 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches…
71 …ion of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-c…
75 …"BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chang…
79 …"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chan…
83 …"BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to …
87 …CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used ins…
91 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
92 "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
95 …"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend…
99 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
100 "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
103 …les in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pi…
107 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
108 "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
111 …"PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limit…
116 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY /…
119 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
123 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Mis…
127 …CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an…
131 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Cl…
132 "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
135 …CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the …
140 "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
143 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
148 …XECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUT…
151 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
155 …"BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the…
156 … "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
159 …CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shor…
164 …"MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + …
167 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
175 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
179 …"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses…
183 …"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misse…
187 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
191 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
199 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
204 "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
211 …"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses …
212 "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS",
215 …"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses…
219 …"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to …
223 …"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to…
235 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
239 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
251 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
255 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
259 …"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external m…
260 …"MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_U…
263 …"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external …
268 …"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\…
271 …-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests …
276 …CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
283 …n": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store …
287 …CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request be…
291 …"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store mis…
292 …etricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STO…
295 …CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performa…
299 …"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due…
303 …CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; …
311 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
315 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
316 …"MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ …
319 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
323 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
324 "MetricExpr": "tma_backend_bound - tma_memory_bound",
327 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
339 … estimates fraction of cycles the CPU performance was potentially limited due to Core computation …
340 …- UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS…
343 …CPU performance was potentially limited due to Core computation issues (non divider-related). Two…
347 …"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any executi…
348 …"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STA…
351 …action of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, P…
355 …ption": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle…
356 …cExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_o…
359 …CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, …
363 …iefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle…
364 …cExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_o…
367 …CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL,…
371 …escription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per c…
372 …"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_…
375 …escription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per c…
379 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
386 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
393 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
400 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
407 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
414 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
415 …HED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT…
421 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads …
428 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads …
435 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
442 …on": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Stor…
449 …his metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simpl…
460 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
464 …raction of slots where the CPU was retiring light-weight operations -- instructions that require n…
465 "MetricExpr": "tma_retiring - tma_heavy_operations",
468 …CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-…
472 …ion": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU h…
476 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
488 …cription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU h…
492 …cription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU h…
496 …cription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU h…
500 …cription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU h…
504 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide v…
508 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide v…
512 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide v…
516 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide v…
520 …": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations --…
524 …ots where the CPU was retiring heavy-weight operations -- instructions that require two or more uo…
528 …"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by…
532 …"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched b…
536 …"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the…
540 …CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long seq…
544 …"BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from…
545 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
548 …CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instr…
552 "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
558 "BriefDescription": "Uops Per Instruction",
564 "BriefDescription": "Instruction per taken branch",
570 "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
576 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
582 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
588 "BriefDescription": "The ratio of Executed- by Issued-Uops",
592 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
595 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
601 "BriefDescription": "Floating Point Operations Per Cycle",
607 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
611 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
614 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
615 …"MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else U…
626 "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
632 "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
638 "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
644 … "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
650 "BriefDescription": "Instruction per taken branch",
656 "BriefDescription": "Branch instructions per taken branch. ",
662 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
668 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
672 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
675 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
679 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
682 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
686 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
689 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
693 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
696 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
700 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
710 "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
716 "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
727 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
733 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
739 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
745 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
751 "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
757 "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
763 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
769 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (inc…
775 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
776 "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
781 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculati…
787 "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
800 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
806 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
812 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
818 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
824 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
830 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
836 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
842 "BriefDescription": "Average CPU Utilization",
854 "BriefDescription": "Giga Floating Point Operations Per Second",
858 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
868 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SM…
879 "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
903 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
909 "BriefDescription": "C3 residency percent per core",
910 "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
915 "BriefDescription": "C6 residency percent per core",
916 "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
921 "BriefDescription": "C7 residency percent per core",
922 "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
927 "BriefDescription": "C2 residency percent per package",
928 "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
933 "BriefDescription": "C3 residency percent per package",
934 "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
939 "BriefDescription": "C6 residency percent per package",
940 "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
945 "BriefDescription": "C7 residency percent per package",
946 "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",