Lines Matching full:including

5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
136 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
142 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
148 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
154 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
160 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data …
166 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
172 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
178 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
184 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
190 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
196 …"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instr…
292 …: "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches…
298 …: "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches…