Lines Matching full:instruction

23     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
76     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
82 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-…
166 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modif…
172 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean…
178 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request m…
184 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests …
190 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request m…
196 …ore to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request h…
226 …"BriefDescription": "The number of 32B fetch windows transferred from IC pipe to DE instruction de…
236 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
241 …"BriefDescription": "The number of 64 byte instruction cache line fulfilled from system memory or …
246 …"BriefDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 …
251     "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs.",
257 …"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instr…
263 …"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instr…
269 …"BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instr…
275 …lidating probes that hit on the instruction stream currently being executed. This would happen if …
280 …"BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any r…
286 …"BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (includin…
292 …"BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (includin…
298 …validated due to L2 invalidating probe (external or LS). The number of instruction cache lines inv…
304 …: "IC line invalidated due to overwriting fill response. The number of instruction cache lines inv…