Lines Matching +full:per +full:- +full:cpu

4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
12 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
13 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
16 …etric represents fraction of slots the CPU was stalled due to Frontend latency issues.  For exampl…
21 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruct…
25 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruc…
30 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruct…
34 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruc…
39 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
43 …CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching o…
48 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
52 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch …
57 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch R…
58 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
61 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch …
66 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new bran…
70 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new bra…
75 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches…
79 …ion of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-c…
84 …"BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chang…
88 …"PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Chan…
93 …"BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to …
97 …CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used ins…
102 …"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend …
103         "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
106 …"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend…
111 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
112         "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
115 …les in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pi…
120 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
121 …"MetricExpr": "(cpu_core@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu_core@INST_DECODED.DECODERS\\,cma…
128 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
129         "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
132 …"PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limit…
137 …"BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limite…
138         "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / CORE_CLKS / 2",
141 …CPU was likely limited due to LSD (Loop Stream Detector) unit.  LSD typically does well sustaining…
147         "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
150 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
155 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Mis…
156 …"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\…
159 …CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an…
164 …"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Cl…
165         "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
168 …CPU has wasted due to Machine Clears.  These slots are either wasted by uops fetched prior to the …
174 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
177 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
183 …"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
186 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
191 …"BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the…
192 …    "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
195 …CPU was stalled without loads missing the L1 data cache.  The L1 data cache typically has the shor…
201 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCL…
204 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
209 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
210         "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
217 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
229 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
234 …"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses…
235 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LO…
238 …"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misse…
243 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
247 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
261 …"BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses …
262         "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CLKS",
265 …"PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses…
270 …"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to …
271         "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CLKS",
274 …"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to…
288 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
289 …MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.…
292 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
306 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
310 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
315 …"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external m…
319 …"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external …
328 …-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests …
334 …CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
342 …n": "This metric estimates how often CPU was stalled  due to RFO store memory accesses; RFO store …
346 …CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request be…
351 …"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store mis…
352 …": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STO…
355 …CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performa…
360 …"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due…
364 …CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; …
373 …resents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granu…
378 …"BriefDescription": "This metric estimates how often CPU was stalled  due to Streaming store memor…
382 …CPU was stalled  due to Streaming store memory accesses; Streaming store optimize out a read reque…
387 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
391 …-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and…
396 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
397         "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
412 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
413         "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
416 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
430 … estimates fraction of cycles the CPU performance was potentially limited due to Core computation …
431 …ask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
434 …CPU performance was potentially limited due to Core computation issues (non divider-related).  Two…
439 …"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any executi…
440 …k\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
443 …action of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, P…
448 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
452 …of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUI…
457 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE In…
461 …"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE I…
466 …"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE I…
483 …ption": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle…
487 …CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, …
492 …iefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle…
496 …CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL,…
501 …escription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per c…
505 …escription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per c…
510 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
518 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
526 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
534 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
542 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
550 …"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on executi…
559 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
562 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
567 …raction of slots where the CPU was retiring light-weight operations -- instructions that require n…
568         "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
571 …CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-…
576 …ion": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU h…
580 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
594 …cription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU h…
598 …cription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU h…
603 …cription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU h…
607 …cription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU h…
612 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide v…
616 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide v…
621 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide v…
625 …This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide v…
630 …his metric represents overall Integer (Int) select operations fraction the CPU has executed (retir…
634 …his metric represents overall Integer (Int) select operations fraction the CPU has executed (retir…
639 …"This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instruct…
647 …"This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instruct…
655 …tric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.",
663 …ion": "This metric represents fraction of slots where the CPU was retiring memory operations -- uo…
671 …on": "This metric represents fraction of slots where the CPU was retiring fused instructions -- wh…
675 …on": "This metric represents fraction of slots where the CPU was retiring fused instructions -- wh…
680 …"BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch in…
681 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / …
684 …etric represents fraction of slots where the CPU was retiring branch instructions that were not fu…
689 …"BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no o…
693 …action of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for …
698 …on": "This metric represents the remaining light uops fraction the CPU has executed - remaining me…
699 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_opera…
706 …": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations --…
707 …"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
710 …ots where the CPU was retiring heavy-weight operations -- instructions that require two or more uo…
715 …"BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructi…
716         "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
719 …of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] f…
724 …"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by…
728 …"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched b…
733 …"BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the…
737 …CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long seq…
742 …"BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a res…
746 …"PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a re…
751 …"BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a res…
755 …the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when …
760 …"BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of h…
768 …"BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from…
769         "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
772 …CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instr…
791 … "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
798 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
805 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
806 … 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR…
812 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
820 …- tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_ica…
826         "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
833         "BriefDescription": "Uops Per Instruction",
840         "BriefDescription": "Instruction per taken branch",
847         "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
854 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
861 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
868 …    "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
875         "BriefDescription": "The ratio of Executed- by Issued-Uops",
879 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
883         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
890         "BriefDescription": "Floating Point Operations Per Cycle",
897 …"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardle…
901 …per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-wi…
905 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
912 …      "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
913 …"MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilizati…
926         "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
933         "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
940         "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
947 …    "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
954         "BriefDescription": "Instruction per taken branch",
961         "BriefDescription": "Branch instructions per taken branch. ",
968 …"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occ…
975 …"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurre…
979 …"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurr…
983 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
987 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
991 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
995 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
999 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
1003 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
1007 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1011 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
1015 …"BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Pre…
1036 …    "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
1043 …"BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for det…
1057         "BriefDescription": "Average number of Uops issued by front-end when it issued something",
1078 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
1085 …"BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_F…
1092 …"BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means highe…
1099 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
1106 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
1113         "BriefDescription": "Fraction of branches that are non-taken conditionals",
1135 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
1142         "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
1148 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1155 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1162         "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
1169 …"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including spe…
1176         "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
1183 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (inc…
1190 …"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads  (inc…
1197 …"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculati…
1198         "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1204 …"BriefDescription": "L2 cache hits per kilo instruction for all demand loads  (including speculati…
1211         "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
1218 …iption": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that me…
1233         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1240         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1247         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1254         "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1261 …      "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1268         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1275         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1282         "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1289         "BriefDescription": "Average CPU Utilization",
1303         "BriefDescription": "Giga Floating Point Operations Per Second",
1307 …ting Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar…
1319 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_o…
1332         "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
1353 …"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from applica…
1450 …"MetricExpr": "(SLOTS - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / SL…
1540         "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)",
1604 …"MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_B…
1612 …"MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_…
1619 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
1620 …"MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM…
1627 …alled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not b…
1628 …"MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_…
1734         "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / SLOTS",
1741 …"BriefDescription": "Counts the number of floating point operations per uop with all default weigh…
1750         "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / SLOTS",
1757 …n": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)",
1761 …ounts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This…
1784         "BriefDescription": "Instructions Per Cycle",
1790         "BriefDescription": "Cycles Per Instruction",
1796         "BriefDescription": "Uops Per Instruction",
1802 …"BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown sto…
1808 …     "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block",
1814         "BriefDescription": "Percentage of total non-speculative loads that are splits",
1820         "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)",
1826 …      "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)",
1832         "BriefDescription": "Instructions per Load",
1838         "BriefDescription": "Instructions per Store",
1844         "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction",
1850         "BriefDescription": "Instructions per Far Branch",
1904         "BriefDescription": "Average CPU Utilization",
1910         "BriefDescription": "Cycle cost per L2 hit",
1916         "BriefDescription": "Cycle cost per LLC hit",
1922         "BriefDescription": "Cycle cost per DRAM hit",
1946         "BriefDescription": "load ops retired per 1000 instruction",
1952         "BriefDescription": "C1 residency percent per core",
1953         "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
1958         "BriefDescription": "C6 residency percent per core",
1959         "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
1964         "BriefDescription": "C7 residency percent per core",
1965         "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
1970         "BriefDescription": "C2 residency percent per package",
1971         "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
1976         "BriefDescription": "C3 residency percent per package",
1977         "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
1982         "BriefDescription": "C6 residency percent per package",
1983         "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
1988         "BriefDescription": "C7 residency percent per package",
1989         "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
1994         "BriefDescription": "C8 residency percent per package",
1995         "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
2000         "BriefDescription": "C9 residency percent per package",
2001         "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
2006         "BriefDescription": "C10 residency percent per package",
2007         "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",