Lines Matching +full:- +full:100
4 …"MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
8 "ScaleUnit": "100%",
13 …etricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
16 …he CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB mi…
17 "ScaleUnit": "100%",
26 "ScaleUnit": "100%",
35 "ScaleUnit": "100%",
43 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
44 "ScaleUnit": "100%",
53 "ScaleUnit": "100%",
58 …"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLE…
62 "ScaleUnit": "100%",
71 "ScaleUnit": "100%",
79 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
80 "ScaleUnit": "100%",
89 "ScaleUnit": "100%",
97 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
98 "ScaleUnit": "100%",
103 "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)",
107 "ScaleUnit": "100%",
112 "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2",
115 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
116 "ScaleUnit": "100%",
120 …"BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active…
121 …"MetricExpr": "(cpu_core@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu_core@INST_DECODED.DECODERS\\,cma…
124 "ScaleUnit": "100%",
129 "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2",
133 "ScaleUnit": "100%",
138 "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / CORE_CLKS / 2",
141 …ly does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be…
142 "ScaleUnit": "100%",
147 "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)",
150 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
151 "ScaleUnit": "100%",
156 …"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\…
159 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
160 "ScaleUnit": "100%",
165 "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)",
168 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
169 "ScaleUnit": "100%",
174 …"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-ret…
177 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
178 "ScaleUnit": "100%",
183 …"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
186 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
187 "ScaleUnit": "100%",
192 … "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
195 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
196 "ScaleUnit": "100%",
201 …mask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCL…
204 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
205 "ScaleUnit": "100%",
209 … the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
210 "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
213 "ScaleUnit": "100%",
217 …"BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB…
221 "ScaleUnit": "100%",
229 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
230 "ScaleUnit": "100%",
235 …"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LO…
239 "ScaleUnit": "100%",
243 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
247 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
248 "ScaleUnit": "100%",
257 "ScaleUnit": "100%",
262 "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CLKS",
266 "ScaleUnit": "100%",
271 "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CLKS",
275 "ScaleUnit": "100%",
284 "ScaleUnit": "100%",
288 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
289 …MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.…
292 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
293 "ScaleUnit": "100%",
302 "ScaleUnit": "100%",
306 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
310 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
311 "ScaleUnit": "100%",
320 "ScaleUnit": "100%",
328 …-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests …
329 "ScaleUnit": "100%",
334 …CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
338 "ScaleUnit": "100%",
342 … CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
346 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
347 "ScaleUnit": "100%",
352 …": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STO…
355 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…
356 "ScaleUnit": "100%",
364 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
365 "ScaleUnit": "100%",
373 …resents rate of split store accesses. Consider aligning your data to the 64-byte cache line granu…
374 "ScaleUnit": "100%",
382 …uired by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there ar…
383 "ScaleUnit": "100%",
387 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
391 …-level data TLB store misses. As with ordinary data caching; focus on improving data locality and…
392 "ScaleUnit": "100%",
396 …tion of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
397 "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
400 "ScaleUnit": "100%",
408 "ScaleUnit": "100%",
412 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
413 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
416 …-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in s…
417 "ScaleUnit": "100%",
426 "ScaleUnit": "100%",
430 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
431 …ask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
434 …-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
435 "ScaleUnit": "100%",
440 …k\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O…
443 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
444 "ScaleUnit": "100%",
448 …"BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled …
452 …ycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; W…
453 "ScaleUnit": "100%",
462 "ScaleUnit": "100%",
470 "ScaleUnit": "100%",
479 "ScaleUnit": "100%",
487 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
488 "ScaleUnit": "100%",
496 …cal Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options…
497 "ScaleUnit": "100%",
506 "ScaleUnit": "100%",
514 "ScaleUnit": "100%",
522 "ScaleUnit": "100%",
530 "ScaleUnit": "100%",
538 "ScaleUnit": "100%",
546 "ScaleUnit": "100%",
554 "ScaleUnit": "100%",
559 …"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retir…
562 …100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typic…
563 "ScaleUnit": "100%",
567 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
568 "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)",
571 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
572 "ScaleUnit": "100%",
576 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
580 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
581 "ScaleUnit": "100%",
590 "ScaleUnit": "100%",
594 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
598 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
599 "ScaleUnit": "100%",
603 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
607 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
608 "ScaleUnit": "100%",
612 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
616 … approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May…
617 "ScaleUnit": "100%",
621 …tric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
625 … approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May…
626 "ScaleUnit": "100%",
635 "ScaleUnit": "100%",
639 …"BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neu…
643 "ScaleUnit": "100%",
647 …"BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neu…
651 "ScaleUnit": "100%",
659 "ScaleUnit": "100%",
663 … represents fraction of slots where the CPU was retiring memory operations -- uops for memory load…
667 "ScaleUnit": "100%",
671 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
675 …represents fraction of slots where the CPU was retiring fused instructions -- where one uop can re…
676 "ScaleUnit": "100%",
681 …"MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / …
684 …lots where the CPU was retiring branch instructions that were not fused. Non-conditional branches …
685 "ScaleUnit": "100%",
693 …o op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address o…
694 "ScaleUnit": "100%",
698 …is metric represents the remaining light uops fraction the CPU has executed - remaining means not …
699 …"MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_opera…
702 "ScaleUnit": "100%",
706 …tric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructio…
707 …"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re…
710 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
711 "ScaleUnit": "100%",
716 "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
719 …t are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the n…
720 "ScaleUnit": "100%",
729 "ScaleUnit": "100%",
734 "MetricExpr": "100 * cpu_core@ASSISTS.ANY\\,umask\\=0x1B@ / SLOTS",
737 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
738 "ScaleUnit": "100%",
747 "ScaleUnit": "100%",
755 …ts. FP Assist may apply when working with very small floating point values (so-called denormals).",
756 "ScaleUnit": "100%",
764 "ScaleUnit": "100%",
769 "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
772 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
773 "ScaleUnit": "100%",
778 …"MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma…
785 …"MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2…
791 … "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
792 …"MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2…
798 …ription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
799 …"MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tm…
805 …Total pipeline cost of branch related instructions (used for program control-flow including functi…
806 …"MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEA…
812 …of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and B…
813 …"MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branch…
820 …100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + …
854 … "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
861 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
868 … "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
875 "BriefDescription": "The ratio of Executed- by Issued-Uops",
879 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
883 "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
897 …BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardles…
901 …-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width…
905 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
912 … "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
913 …"MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilizati…
983 …"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower num…
987 …"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower nu…
991 …"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower num…
995 …"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower nu…
999 …"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mean…
1003 …"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number mea…
1007 …"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means h…
1011 …"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means …
1036 … "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions",
1057 "BriefDescription": "Average number of Uops issued by front-end when it issued something",
1078 …tion": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_…
1085 …"BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_F…
1086 …"MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switch…
1092 …"BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means highe…
1099 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
1106 …"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative b…
1113 "BriefDescription": "Fraction of branches that are non-taken conditionals",
1135 …"MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR…
1142 "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)",
1148 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
1155 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
1198 "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
1218 … instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
1233 "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
1240 "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
1247 "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
1254 "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
1261 … "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
1268 "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
1275 "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
1282 "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
1307 … supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.…
1319 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_o…
1364 "ScaleUnit": "100%",
1372 "ScaleUnit": "100%",
1380 "ScaleUnit": "100%",
1388 "ScaleUnit": "100%",
1397 "ScaleUnit": "100%",
1405 "ScaleUnit": "100%",
1413 "ScaleUnit": "100%",
1421 "ScaleUnit": "100%",
1429 "ScaleUnit": "100%",
1437 "ScaleUnit": "100%",
1445 "ScaleUnit": "100%",
1450 …"MetricExpr": "(SLOTS - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / SL…
1454 "ScaleUnit": "100%",
1462 "ScaleUnit": "100%",
1470 "ScaleUnit": "100%",
1478 "ScaleUnit": "100%",
1486 "ScaleUnit": "100%",
1494 "ScaleUnit": "100%",
1502 "ScaleUnit": "100%",
1510 "ScaleUnit": "100%",
1518 "ScaleUnit": "100%",
1526 "ScaleUnit": "100%",
1535 "ScaleUnit": "100%",
1540 "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)",
1543 "ScaleUnit": "100%",
1551 "ScaleUnit": "100%",
1559 "ScaleUnit": "100%",
1567 "ScaleUnit": "100%",
1575 "ScaleUnit": "100%",
1583 "ScaleUnit": "100%",
1591 "ScaleUnit": "100%",
1599 "ScaleUnit": "100%",
1604 …"MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_B…
1607 "ScaleUnit": "100%",
1612 …"MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_…
1615 "ScaleUnit": "100%",
1619 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
1620 …"MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM…
1623 "ScaleUnit": "100%",
1627 …alled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not b…
1628 …"MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_…
1631 "ScaleUnit": "100%",
1640 "ScaleUnit": "100%",
1649 "ScaleUnit": "100%",
1657 "ScaleUnit": "100%",
1665 "ScaleUnit": "100%",
1673 "ScaleUnit": "100%",
1681 "ScaleUnit": "100%",
1689 "ScaleUnit": "100%",
1697 "ScaleUnit": "100%",
1705 "ScaleUnit": "100%",
1713 "ScaleUnit": "100%",
1721 "ScaleUnit": "100%",
1729 "ScaleUnit": "100%",
1734 "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / SLOTS",
1737 "ScaleUnit": "100%",
1745 "ScaleUnit": "100%",
1750 "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / SLOTS",
1753 "ScaleUnit": "100%",
1757 …n": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)",
1761 …ounts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This…
1762 "ScaleUnit": "100%",
1802 …"BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown sto…
1803 "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS",
1808 … "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block",
1809 "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS",
1814 "BriefDescription": "Percentage of total non-speculative loads that are splits",
1815 "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS",
1844 "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction",
1869 "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL",
1875 "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL",
1881 "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL",
1887 "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL",
1929 "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
1935 "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
1941 "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
1953 "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",
1959 "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
1965 "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
1971 "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
1977 "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
1983 "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
1989 "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
1995 "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",
2001 "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",
2007 "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",