Lines Matching full:another

50 … "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on …
205 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L…
225 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G…
320 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
385 …"BriefDescription": "Duration in cycles to reload either shared or modified data from another core…
510 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the …
565 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
735 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the …
840 …n": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on …
910 …"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on t…
1015 …n": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 o…
1055 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a…
1060 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr…
1155 …ossible for a translation. The source could be local/remote/distant memory or another core's cache"
1205 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L3 on…
1210 …sor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a…
1305 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
1315 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G…
1435 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
1485 …e processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on …
1550 …e processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the …
1615 …sary for this translation. The source could be local/remote/distant memory or another core's cache"
1675 …ion": "TM aborted because a conflict occurred with a non-transactional access by another processor"
1685 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …
1710 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
1775     "BriefDescription": "TM aborted because a conflict occurred with another transaction."
1815 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 o…
1850     "BriefDescription": "TM Store (fav or non-fav) caused another thread to fail"
1895 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
1900 …"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or…
1915 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
1950 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
2010 …": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the …
2030 …ic because they always span at least 2 slices.  If a snoop or store from another thread changes th…
2055 … processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a…
2060 … Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on t…
2155     "BriefDescription": "TM Load (fav) caused another thread to fail"
2220 …n": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the …