Lines Matching full:load
297 "BriefDescription": "Cycles stalled by LSU load finishes",
492 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 experienced a Load-Hi…
504 …"BriefDescription": "Percentage of L2 load hits per instruction where the L2 did not experience a …
510 …riefDescription": "Percentage of L2 load hits per instruction where the L2 experienced some confli…
534 …"BriefDescription": "Percentage of L3 load hits per instruction where the load collided with a pen…
546 …"BriefDescription": "Percentage of L3 load hits per instruction where the L3 did not experience a …
594 "BriefDescription": "Percentage of L1 demand load misses per run instruction",
642 "BriefDescription": "Percentage of DL1 reloads from L2 with a Load-Hit-Store conflict",
654 …"BriefDescription": "Percentage of DL1 reloads from L2 with some conflict other than Load-Hit-Stor…
678 …"BriefDescription": "Percentage of DL1 reloads from L3 where the load collided with a pending pref…
684 …"BriefDescription": "Percentage of L3 load hits per instruction where the line was brought into th…
948 "BriefDescription": "Percentage of L1 load misses per L1 load ref",
972 "BriefDescription": "L2 dmand Load Miss Rate (per run instruction)(%)",
996 "BriefDescription": "L3 demand Load Miss Rate (per run instruction)(%)",
1368 …"BriefDescription": "Average number of cycles LRQ stays active for one load. Slot 0 is VALID ONLY…
1374 …"BriefDescription": "Average number of cycles LRQ stays active for one load. Slot 43 is valid ONL…
1380 …"BriefDescription": "Average number of cycles SRQ stays active for one load. Slot 0 is VALID ONLY…
1386 …"BriefDescription": "Average number of cycles SRQ stays active for one load. Slot 39 is valid ONL…
1404 "BriefDescription": "Marked L2L3 remote Load latency",
1410 "BriefDescription": "Marked L2L3 distant Load latency",
1416 "BriefDescription": "Distant L4 average load latency",
1422 "BriefDescription": "Marked Dmem Load latency",
1428 …"BriefDescription": "estimated exposed miss latency for dL1 misses, ie load miss when we were NTC",
1434 …"BriefDescription": "Average load latency for all marked demand loads that came from L2.1 in the M…
1440 …"BriefDescription": "Average load latency for all marked demand loads that came from L2.1 in the S…
1446 …n": "Average load latency for all marked demand loads that came from the L2 and suffered a conflic…
1452 …n": "Average load latency for all marked demand loads that came from the L2 and suffered a conflic…
1458 … "BriefDescription": "Average load latency for all marked demand loads that came from the L2",
1464 …"BriefDescription": "Average load latency for all marked demand loads that were satisfied by lines…
1470 …"BriefDescription": "Average load latency for all marked demand loads that came from the L2 and su…
1476 …"BriefDescription": "Average load latency for all marked demand loads that came from the L3 and be…
1482 "BriefDescription": "Marked L31 Load latency",
1488 "BriefDescription": "Marked L31 Load latency",
1494 … "BriefDescription": "Average load latency for all marked demand loads that came from the L3",
1500 …"BriefDescription": "Average load latency for all marked demand loads that came from the L3 and su…
1506 …"BriefDescription": "Average load latency for all marked demand loads that come from beyond the L3…
1518 "BriefDescription": "Local L4 average load latency",
1524 "BriefDescription": "Marked Lmem Load latency",
1542 "BriefDescription": "Marked L2L3 remote Load latency",
1548 "BriefDescription": "Marked L2L3 remote Load latency",
1554 "BriefDescription": "Remote L4 average load latency",
1560 "BriefDescription": "Marked Rmem Load latency",
1926 …"Fraction of hits on any Centaur (local, remote, or distant) on either L4 or DRAM per L1 load ref",
1946 … "BriefDescription": "Fraction of hits on a distant chip's Centaur (L4 or DRAM) per L1 load ref",
1971 … of a line in the M (exclusive) state on the L2 or L3 of a core on a distant chip per L1 load ref",
1976 …tion of hits of a line in the S state on the L2 or L3 of a core on a distant chip per L1 load ref",
1981 "BriefDescription": "Fraction of hits on a distant Centaur's cache per L1 load ref",
1986 "BriefDescription": "Fraction of hits on a distant Centaur's DRAM per L1 load ref",
2006 …escription": "Total Fixed point operations executded in the Load/Store Unit following a load/store…
2036 "BriefDescription": "Fraction of L1 hits per load ref",
2041 "BriefDescription": "Fraction of L1 load misses per L1 load ref",
2046 … "BriefDescription": "Fraction of hits on another core's L2 on the same chip per L1 load ref",
2051 …f hits of a line in the M (exclusive) state on another core's L2 on the same chip per L1 load ref",
2056 … "Fraction of hits of a line in the S state on another core's L2 on the same chip per L1 load ref",
2066 "BriefDescription": "Fraction of L2 load hits per L1 load ref",
2071 "BriefDescription": "Fraction of L2 load misses per L1 load ref",
2076 …"BriefDescription": "Fraction of L2 load hits per L1 load ref where the L2 experienced a Load-Hit-…
2081 …"BriefDescription": "Fraction of L2 load hits per L1 load ref where the L2 did not experience a co…
2086 …"BriefDescription": "Fraction of L2 load hits per L1 load ref where the L2 experienced some confli…
2101 "BriefDescription": "Marked L31 Load latency",
2106 … "BriefDescription": "Fraction of hits on another core's L3 on the same chip per L1 load ref",
2111 …f hits of a line in the M (exclusive) state on another core's L3 on the same chip per L1 load ref",
2116 … "Fraction of hits of a line in the S state on another core's L3 on the same chip per L1 load ref",
2121 …"BriefDescription": "Fraction of L3 load hits per load ref where the demand load collided with a p…
2126 "BriefDescription": "Fraction of L3 load hits per L1 load ref",
2131 "BriefDescription": "Fraction of L3 load misses per L1 load ref",
2136 …"BriefDescription": "Fraction of L3 load hits per load ref where the L3 did not experience a confl…
2141 …"BriefDescription": "Fraction of L3 hits on lines that were not in the MEPF state per L1 load ref",
2146 …action of L3 hits on lines that were recently prefetched into the L3 (MEPF state) per L1 load ref",
2151 "BriefDescription": "Fraction of hits on a local Centaur's cache per L1 load ref",
2156 "BriefDescription": "Fraction of hits on a local Centaur's DRAM per L1 load ref",
2161 "BriefDescription": "Fraction of hits on a local Centaur (L4 or DRAM) per L1 load ref",
2171 …action of hits on another core's L2 or L3 on a different chip (remote or distant) per L1 load ref",
2176 …"BriefDescription": "Fraction of hits on another core's L2 or L3 on the same chip per L1 load ref",
2181 … "BriefDescription": "Fraction of hits on a remote chip's Centaur (L4 or DRAM) per L1 load ref",
2191 …s of a line in the M (exclusive) state on the L2 or L3 of a core on a remote chip per L1 load ref",
2196 …ction of hits of a line in the S state on the L2 or L3 of a core on a remote chip per L1 load ref",
2201 "BriefDescription": "Fraction of hits on a remote Centaur's cache per L1 load ref",
2206 "BriefDescription": "Fraction of hits on a remote Centaur's DRAM per L1 load ref",