Lines Matching full:in
10 "BriefDescription": "LSU Finished an internal operation in LD0 port."
20 "BriefDescription": "LSU Finished an internal operation in ST0 port."
25 "BriefDescription": "LSU Finished an internal operation in ST4 port."
30 "BriefDescription": "Cycles in which an instruction reload is pending to satisfy a demand miss."
45 …riefDescription": "Cycles in which the oldest instruction in the pipeline finished at dispatch and…
60 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a lwsync waiting t…
75 "BriefDescription": "Cycles when the run latch is set and the core is in ST mode."
80 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was dispatched but not…
85 "BriefDescription": "Cycles when the thread is in Hypervisor state. MSR[S HV PR]=010."
90 "BriefDescription": "LSU Finished an internal operation in LD1 port."
95 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline required special handl…
100 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load…
105 "BriefDescription": "LSU Finished an internal operation in ST1 port."
115 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the V…
120 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a stcx waiting for…
125 …in which the oldest instruction in the pipeline was executing in any unit before it was flushed. N…
135 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. Note t…
150 …in which the oldest instruction in the pipeline was waiting to finish in one of the execution unit…
155 "BriefDescription": "LSU Finished an internal operation in ST2 port."
175 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for the no…
180 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a simple fixed poi…
185 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was not allowed to com…
195 …"BriefDescription": "TLBIE instructions finished in the LSU. Two TLBIEs can finish each cycle. All…
215 …in which both instructions in the ICT entry pair show as finished. These are the cycles between fi…
225 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered an ERAT miss …
230 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline cannot complete becaus…
235 "BriefDescription": "LSU Finished an internal operation in ST3 port."
240 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the B…
245 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a hwsync waiting f…
250 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a TLBIEL instructi…
255 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline completed without an n…