Lines Matching full:instruction

5 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or…
10 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any other reason."
30 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
35 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because of power mana…
40 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the STF mappe…
45 …"BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access)…
50 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
65     "BriefDescription": "Cycles in which at least one instruction is completed by this thread."
80 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch due to Issue queue fu…
85     "BriefDescription": "Marked instruction RC dispatched in L2."
90 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the L…
95 …"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT…
100 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
115 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the XVFC mapp…
120 …"BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was rel…
125 …S_DISP / PM_INST_DISP will show the average number of internal operations per PowerPC instruction."
130 …"BriefDescription": "An instruction issued and the issue was later cancelled. Only one cancel per …
135     "BriefDescription": "Branch Taken instruction completed."
140 …ycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not…
145 …"BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction TLB …
150 …"BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not co…
155 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instructio…
160 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch while waiting on the …
165 …"BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cach…
170     "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."
175 …"BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Tab…
180 …ycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."
185 …"BriefDescription": "Cycles in which the NTC instruction is held at dispatch because the mapper/SR…
190 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the l…
195 …s finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an ad…
205 …"BriefDescription": "The processor's instruction cache was reloaded from a source other than the l…
210 …"BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after …
215 …"BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instru…
220 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sourc…
230 …"BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any s…
235     "BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason."
240 …efDescription": "Cycles in which the NTC instruction is held at dispatch because of a synchronizin…