Lines Matching refs:accesses
33 for cachelines with highest contention - highest number of HITM accesses.
186 - cacheline percentage of all Remote/Local HITM accesses
189 - cacheline percentage of all peer accesses
198 - sum of all cachelines accesses
201 - sum of all load accesses
204 - sum of all store accesses
207 L1Hit - store accesses that hit L1
208 L1Miss - store accesses that missed L1
209 N/A - store accesses with memory level is not available
215 - count of LLC load accesses, includes LLC hits and LLC HITMs
218 - count of remote load accesses, includes remote hits and remote HITMs;
219 on Arm neoverse cores, RmtHit is used to account remote accesses,
223 - count of local and remote DRAM accesses
228 - % of Remote/Local HITM accesses for given offset within cacheline
231 - % of Remote/Local peer accesses for given offset within cacheline
234 - % of store accesses that hit L1, missed L1 and N/A (no available) memory
241 - pid of the process responsible for the accesses
244 - tid of the process responsible for the accesses
247 - code address responsible for the accesses
250 - sum of cycles for given accesses - Remote/Local HITM and generic load
253 - sum of cycles for given accesses - Remote/Local peer load and generic load
272 The 'Node' field displays nodes that accesses given cacheline
305 - overall statistics of memory accesses