Lines Matching full:stores
102 device, stores it in a buffer, and sets a flag to indicate the buffer
134 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
140 This pattern of memory accesses, where one CPU stores values to two
197 it, as loads can obtain values only from earlier stores.
202 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
206 P0 stores 1 to buf before storing 1 to flag, since it executes
222 each CPU stores to its own shared location and then loads from the
270 W: P0 stores 1 to flag executes before
273 Z: P0 stores 1 to buf executes before
274 W: P0 stores 1 to flag.
296 Write events correspond to stores to shared memory, such as
398 executed before either of the stores to y. However, a compiler could
399 lift the stores out of the conditional, transforming the code into
600 from both of P0's stores. It is possible to handle mixed-size and
612 shared memory, the stores to that location must form a single global
618 the stores to x is simply the order in which the stores overwrite one
625 stores reach x's location in memory (or if you prefer a more
626 hardware-centric view, the order in which the stores get written to
636 and W' are two stores, then W ->co W'.
723 just like with the rf relation, we distinguish between stores that
724 occur on the same CPU (internal coherence order, or coi) and stores
727 On the other hand, stores to different memory locations are never
758 stores to x, there would also be fr links from the READ_ONCE() to
784 only internal operations. However, loads, stores, and fences involve
809 time to process the stores that it receives, and a store can't be used
811 most architectures, the local caches process stores in
838 smp_wmb() forces the CPU to execute all po-earlier stores
839 before any po-later stores;
852 propagates stores. When a fence instruction is executed on CPU C:
854 For each other CPU C', smp_wmb() forces all po-earlier stores
855 on C to propagate to C' before any po-later stores do.
859 stores executed on C) is forced to propagate to C' before the
863 executed (including all po-earlier stores on C) is forced to
868 affects stores from other CPUs that propagate to CPU C before the
869 fence is executed, as well as stores that are executed on C before the
872 A-cumulative; they only affect the propagation of stores that are
888 E and F are both stores on the same CPU and an smp_wmb() fence
897 The operational model requires that whenever W and W' are both stores
918 operations really are atomic, that is, no other stores can
924 Propagation: This requires that certain stores propagate to
946 According to the principle of cache coherence, the stores to any fixed
986 CPU 0 stores 14 to x;
987 CPU 1 stores 14 to x;
1001 there must not be any stores coming between W' and W in the coherence
1027 X and Y are both stores and an smp_wmb() fence occurs between
1161 stores do reach P1's local cache in the proper order, it can happen
1170 incoming stores in FIFO order. By contrast, other architectures
1179 the stores it has already received. Thus, if the code was changed to:
1200 outstanding stores have been processed by the local cache. In the
1202 po-earlier stores to propagate to every other CPU in the system; then
1203 it has to wait for the local cache to process all the stores received
1204 as of that time -- not just the stores received when the strong fence
1230 W ->coe W'. This means that W and W' are stores to the same location,
1234 the other is made later by the memory subsystem. When the stores are
1276 read from different stores:
1324 stores. If r1 = 1 and r2 = 0 at the end then there is a prop link
1387 guarantees that the stores to x and y both propagate to P0 before the
1542 In the kernel's implementations of RCU, the requirements for stores
1813 This requires P0 and P2 to execute their loads and stores out of
1928 and some other stores W and W' occur po-before the lock-release and
2117 cumul-fence memory barriers force stores that are po-before
2118 the barrier to propagate to other CPUs before stores that are
2125 strong-fence memory barriers force stores that are po-before
2277 (i.e., smp_rmb()) and some affect only stores (smp_wmb()); otherwise
2359 stores will propagate to P1 in that order. However, rcu_dereference()
2415 Do the plain stores to y race? Clearly not if P1 reads a non-zero
2427 before the second can execute. Therefore the two stores cannot be
2432 race-candidate stores W and W', where W ->co W', the LKMM says the
2433 stores don't race if W can be linked to W' by a
2616 will self-deadlock in the executions where it stores 36 in y.