Lines Matching full:coherence
19 11. CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
606 CACHE COHERENCE AND THE COHERENCE ORDER RELATION: co, coi, and coe
609 Cache coherence is a general principle requiring that in a
613 ordering which all the CPUs agree on (the coherence order), and this
617 To put it another way, for any variable x, the coherence order (co) of
620 comes first in the coherence order; the store which directly
624 You can think of the coherence order as being the order in which the
628 coherence order, that is, if the value stored by W gets overwritten,
631 Coherence order is required to be consistent with program order. This
634 Write-write coherence: If W ->po-loc W' (i.e., W comes before
638 Write-read coherence: If W ->po-loc R, where W is a store and R
640 which comes after W in the coherence order.
642 Read-write coherence: If R ->po-loc W, where R is a load and W
644 W in the coherence order.
646 Read-read coherence: If R ->po-loc R', where R and R' are two
649 coherence order.
654 Wikipedia, sequential consistency per variable and cache coherence
655 mean the same thing except that cache coherence includes an extra
658 Any reasonable memory model will include cache coherence. Indeed, our
659 expectation of cache coherence is so deeply ingrained that violations
673 write-write coherence rule: Since the store of 23 comes later in
674 program order, it must also come later in x's coherence order and
687 If r1 = 666 at the end, this would violate the read-write coherence
690 coming earlier in the coherence order (in this case, x's initial
710 would violate the read-read coherence rule: The r1 load comes before
712 comes later in the coherence order.
724 occur on the same CPU (internal coherence order, or coi) and stores
725 that occur on different CPUs (external coherence order, or coe).
729 related by po. Coherence order is strictly per-location, or if you
730 prefer, each location has its own independent coherence order.
741 the coherence order.
755 The value loaded from x will be 0 (assuming cache coherence!), and it
792 store falls in the location's coherence order. In particular, it must
908 maintaining cache coherence and the fact that a CPU can't operate on a
931 Plain-coherence: This requires that plain memory accesses
933 the operational model's rules regarding cache coherence.
938 "rcu" and "plain-coherence" axioms are specific to the LKMM.
946 According to the principle of cache coherence, the stores to any fixed
958 "coherence" axiom expresses this by requiring the union of these
966 cache coherence demands.
993 problem is that the position of CPU 0's store in x's coherence order
1001 there must not be any stores coming between W' and W in the coherence
1109 violation of the read-write coherence rule. Similarly, if we had
1114 W' before W in the coherence order. It would effectively cause W to
1115 overwrite W', in violation of the write-write coherence rule.
1118 violating the write-write coherence rule by requiring the CPU not to
1231 they execute on different CPUs, and W comes before W' in the coherence
1244 cache coherence. The relation is called prop, and it links two events
1246 the first event in the coherence order and propagates to C before the
1272 event, because P1's store came after P0's store in x's coherence
1406 store is coherence-later than E and propagates to every CPU and to RAM
1425 Thus W, which comes later than E in the coherence order, will
1435 coherence order, contradicting the fact that E ->coe W. If E was a
2472 called the "plain-coherence" axiom because of their resemblance to the
2473 rules used by the operational model to ensure cache coherence (that
2476 fall in the coherence order):
2486 load must read from that store or one coherence-after it).
2491 the second must come after the first in the coherence order).