Lines Matching refs:EAX
5 0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported subleafs
8 1, 0, EAX, 3:0, stepping, Stepping ID
9 1, 0, EAX, 7:4, model, Model
10 1, 0, EAX, 11:8, family, Family ID
11 1, 0, EAX, 13:12, processor, Processor Type
12 1, 0, EAX, 19:16, model_ext, Extended Model ID
13 1, 0, EAX, 27:20, family_ext, Extended Family ID
92 4, 0, EAX, 4:0, cache_type, Cache type like instr/data or unified
93 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1)
94 4, 0, EAX, 8, cache_self_init, Cache Self Initialization
95 4, 0, EAX, 9, fully_associate, Fully Associative cache
96 # 4, 0, EAX, 13:10, resvd, resvd
97 …4, 0, EAX, 25:14, max_logical_id, Max number of addressable IDs for logical processors sharin…
98 … 4, 0, EAX, 31:26, max_phy_id, Max number of addressable IDs for processors in phy package
110 5, 0, EAX, 15:0, min_mon_size, Smallest monitor line size in bytes
126 6, 0, EAX, 0, dig_temp, Digital temperature sensor supported
127 6, 0, EAX, 1, turbo, Intel Turbo Boost
128 6, 0, EAX, 2, arat, Always running APIC timer
129 # 6, 0, EAX, 3, resv, Reserved
130 6, 0, EAX, 4, pln, Power limit notifications supported
131 6, 0, EAX, 5, ecmd, Clock modulation duty cycle extension supported
132 6, 0, EAX, 6, ptm, Package thermal management supported
133 6, 0, EAX, 7, hwp, HWP base register
134 6, 0, EAX, 8, hwp_notify, HWP notification
135 6, 0, EAX, 9, hwp_act_window, HWP activity window
136 6, 0, EAX, 10, hwp_energy, HWP energy performance preference
137 6, 0, EAX, 11, hwp_pkg_req, HWP package level request
138 # 6, 0, EAX, 12, resv, Reserved
139 6, 0, EAX, 13, hdc, HDC base registers supported
140 6, 0, EAX, 14, turbo3, Turbo Boost Max 3.0
141 6, 0, EAX, 15, hwp_cap, Highest Performance change supported
142 6, 0, EAX, 16, hwp_peci, HWP PECI override is supported
143 6, 0, EAX, 17, hwp_flex, Flexible HWP is supported
144 6, 0, EAX, 18, hwp_fast, Fast access mode for the IA32_HWP_REQUEST MSR is supported
145 # 6, 0, EAX, 19, resv, Reserved
146 6, 0, EAX, 20, hwp_ignr, Ignoring Idle Logical Processor HWP request is supported
216 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version
217 0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU
218 0xA, 0, EAX, 23:16, pmu_cnt_bits, Bit wideth of PMU counter
219 0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to enumerate PMU events
236 …0xB, 0, EAX, 4:0, id_shift, Number of bits to shift right on x2APIC ID to get a unique topo…
245 0xD, 0, EAX, 0, x87, X87 state
246 0xD, 0, EAX, 1, sse, SSE state
247 0xD, 0, EAX, 2, avx, AVX state
248 0xD, 0, EAX, 4:3, mpx, MPX state
249 0xD, 0, EAX, 7:5, avx512, AVX-512 state
250 0xD, 0, EAX, 9, pkru, PKRU state
255 0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available
256 0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported
257 0xD, 1, EAX, 2, xgetbv, XGETBV supported
258 0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS supported
291 0x12, 0, EAX, 0, sgx1, L3 Cache Allocation supported
292 0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported
302 … 0x15, 0, EAX, 31:0, tsc_denominator, The denominator of the TSC/”core crystal clock” ratio
309 0x16, 0, EAX, 15:0, cpu_base_freq, Processor Base Frequency in MHz
316 0x17, 0, EAX, 31:0, max_socid, Maximum input value of supported sub-leaf
333 0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core
378 0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits
379 0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits
383 # EAX: Extended APIC ID
384 0x8000001E, 0, EAX, 31:0, extended_apic_id, Extended APIC ID
393 0x8000001F, 0, EAX, 0, sme, Secure Memory Encryption
394 0x8000001F, 0, EAX, 1, sev, Secure Encrypted Virtualization
395 0x8000001F, 0, EAX, 2, vmpgflush, VM Page Flush MSR
396 0x8000001F, 0, EAX, 3, seves, SEV Encrypted State