Lines Matching +full:7 +full:c
9 1, 0, EAX, 7:4, model, Model
15 1, 0, EBX, 7:0, brand, Brand Index
27 1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology
58 1, 0, EDX, 7, mce, Machine Check Exception
93 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1)
114 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT
115 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT
116 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT
117 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT
118 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT
119 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
120 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT
121 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT
133 6, 0, EAX, 7, hwp, HWP base register
157 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE supported
158 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported
159 7, 0, EBX, 2, sgx, Software Guard Extensions
160 7, 0, EBX, 3, bmi1, BMI1
161 7, 0, EBX, 4, hle, Hardware Lock Elision
162 7, 0, EBX, 5, avx2, AVX2
163 # 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only on x87 exceptions
164 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention
165 7, 0, EBX, 8, bmi2, BMI2
166 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB
167 7, 0, EBX, 10, invpcid, INVPCID instruction
168 7, 0, EBX, 11, rtm, Restricted Transactional Memory
169 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability
170 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS
171 7, 0, EBX, 14, mpx, Memory Protection Extensions
172 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability
173 7, 0, EBX, 16, avx512f, AVX512 Foundation instr
174 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr
175 7, 0, EBX, 18, rdseed, RDSEED instr
176 7, 0, EBX, 19, adx, ADX instr
177 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention
178 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add
179 # 7, 0, EBX, 22, resvd, resvd
180 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr
181 7, 0, EBX, 24, clwb, CLWB instr
182 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr
183 7, 0, EBX, 26, avx512pf, Prefetch
184 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
185 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
186 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
187 7, 0, EBX, 26, avx512bw, AVX512 Byte & Word instr
188 7, 0, EBX, 28, avx512vl, AVX512 Vector Length Extentions (VL)
189 7, 0, ECX, 0, prefetchwt1, X
190 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
191 7, 0, ECX, 2, umip, User-mode Instruction Prevention
193 7, 0, ECX, 3, pku, Protection Keys for User-mode pages
194 7, 0, ECX, 4, ospke, CR4 PKE set to enable protection keys
195 # 7, 0, ECX, 16:5, resvd, resvd
196 …7, 0, ECX, 21:17, mawau, The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-…
197 7, 0, ECX, 22, rdpid, RDPID and IA32_TSC_AUX
198 # 7, 0, ECX, 29:23, resvd, resvd
199 7, 0, ECX, 30, sgx_lc, SGX Launch Configuration
200 # 7, 0, ECX, 31, resvd, resvd
216 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version
249 0xD, 0, EAX, 7:5, avx512, AVX-512 state
366 0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes
378 0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits
386 0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID
389 0x8000001E, 0, ECX, 7:0, node_id, Node ID
397 0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable memory encryption