Lines Matching refs:X86_BUG
426 #define X86_BUG(x) (NCAPINTS*32 + (x)) macro
428 #define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
429 #define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
430 #define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
431 #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
432 #define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
433 #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
434 #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
435 #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
436 #define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
442 #define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
444 #define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
445 #define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
446 #define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
447 #define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
448 #define X86_BUG_CPU_MELTDOWN X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel pa…
449 #define X86_BUG_SPECTRE_V1 X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditi…
450 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirec…
451 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack…
452 #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
453 #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
454 #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */
455 #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
456 #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
457 #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute chang…
458 #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
459 #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulner…
460 #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unkno…
461 #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */
462 #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */