Lines Matching +full:24 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
67 (((x) >> 24) & 0x000000ff))
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
133 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
255 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
262 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
270 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
278 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
280 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
286 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
288 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
296 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
303 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
307 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
313 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
316 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
341 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
342 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
343 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
344 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
345 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
346 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
347 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
387 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
388 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
390 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
413 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
452 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
453 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
454 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
455 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
456 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
457 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
458 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
459 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
460 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
461 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
462 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
463 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
464 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
487 * n: 0-15
493 * n: 0-15
554 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
560 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
561 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
673 #define SCTLR_EL1_E0E (BIT(24))
679 #define SCTLR_EL1_UMA (BIT(9))
742 #define ID_AA64ISAR1_GPA_SHIFT 24
776 #define ID_AA64PFR0_GIC_SHIFT 24
841 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
887 #define ID_AA64MMFR1_SPECSEI_SHIFT 24
907 #define ID_AA64MMFR2_NV_SHIFT 24
937 #define ID_DFR0_PERFMON_SHIFT 24
945 #define ID_ISAR4_PSR_M_SHIFT 24
955 #define ID_ISAR0_DIVIDE_SHIFT 24
963 #define ID_ISAR5_RDM_SHIFT 24
970 #define ID_ISAR6_I8MM_SHIFT 24
979 #define ID_MMFR0_FCSE_SHIFT 24
988 #define ID_MMFR4_CCIDX_SHIFT 24
998 #define ID_PFR0_DIT_SHIFT 24
1005 #define ID_DFR0_PERFMON_SHIFT 24
1017 #define MVFR0_FPSHVEC_SHIFT 24
1026 #define MVFR1_FPHP_SHIFT 24
1035 #define ID_PFR1_VIRT_FRAC_SHIFT 24
1072 #define ZCR_ELx_LEN_SIZE 9
1120 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1150 #define ICH_VMCR_EOIM_SHIFT 9
1156 #define ICH_VMCR_PMR_SHIFT 24
1176 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
1180 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1200 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1270 * set mask are set. Other bits are left as-is.