Lines Matching +full:0 +full:- +full:3
1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
26 #define Op0_mask 0x3
28 #define Op1_mask 0x7
30 #define CRn_mask 0xf
32 #define CRm_mask 0xf
34 #define Op2_mask 0x7
64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
65 (((x) << 8) & 0x00ff0000) | \
66 (((x) >> 8) & 0x0000ff00) | \
67 (((x) >> 24) & 0x000000ff))
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
83 * Op0 = 0, CRn = 4
86 * Rt = 0x1f
91 #define PSTATE_PAN pstate_field(0, 4)
92 #define PSTATE_UAO pstate_field(0, 3)
93 #define PSTATE_SSBS pstate_field(3, 1)
94 #define PSTATE_TCO pstate_field(3, 4)
96 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
97 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
98 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
99 #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
106 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
108 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
110 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
111 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
112 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
118 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
119 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
120 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
121 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
122 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
123 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
124 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
125 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
126 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
127 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
128 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
129 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
130 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
131 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
132 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
133 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
134 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
135 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
136 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
137 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
138 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
139 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
141 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
142 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
143 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
145 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
146 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
147 #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
148 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
149 #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
150 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
151 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
152 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
153 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
154 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
155 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
156 #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
158 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
159 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
160 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
161 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
162 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
163 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
164 #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
166 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
167 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
168 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
170 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
171 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
172 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
174 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
175 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
177 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
178 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
180 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
181 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
183 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
184 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
185 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
187 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
188 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
189 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
190 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
191 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
193 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
194 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
196 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
197 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
198 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
200 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
201 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
202 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
203 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
205 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
206 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
207 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
208 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
210 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
211 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
213 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
214 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
216 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
218 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
219 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
220 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
222 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
223 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
224 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
225 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
226 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
227 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
228 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
229 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
230 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
231 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
233 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
234 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
236 #define SYS_PAR_EL1_F BIT(0)
241 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
242 #define SYS_PMSIDR_EL1_FE_SHIFT 0
245 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
249 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
251 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
253 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
255 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
256 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
257 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
262 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
263 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
265 #define SYS_PMSCR_EL1_CX_SHIFT 3
270 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
271 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
273 #define SYS_PMSCR_EL2_CX_SHIFT 3
278 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
280 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
281 #define SYS_PMSIRR_EL1_RND_SHIFT 0
283 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
286 #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1)
288 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
289 #define SYS_PMSFCR_EL1_FE_SHIFT 0
296 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
299 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
303 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
304 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
307 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
308 #define SYS_PMBLIMITR_EL1_E_SHIFT 0
310 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
311 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
313 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
316 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
322 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
324 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
325 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
326 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
328 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
329 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
331 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
332 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
334 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
341 #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
342 #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
343 #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
344 #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
345 #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
346 #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
347 #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
349 #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
352 #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
353 #define TRBLIMITR_TRIG_MODE_SHIFT 3
354 #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
356 #define TRBLIMITR_ENABLE BIT(0)
357 #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
358 #define TRBPTR_PTR_SHIFT 0
359 #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
361 #define TRBSR_EC_MASK GENMASK(5, 0)
368 #define TRBSR_MSS_MASK GENMASK(15, 0)
369 #define TRBSR_MSS_SHIFT 0
370 #define TRBSR_BSC_MASK GENMASK(5, 0)
371 #define TRBSR_BSC_SHIFT 0
372 #define TRBSR_FSC_MASK GENMASK(5, 0)
373 #define TRBSR_FSC_SHIFT 0
374 #define TRBMAR_SHARE_MASK GENMASK(1, 0)
376 #define TRBMAR_OUTER_MASK GENMASK(3, 0)
378 #define TRBMAR_INNER_MASK GENMASK(3, 0)
379 #define TRBMAR_INNER_SHIFT 0
380 #define TRBTRG_TRG_MASK GENMASK(31, 0)
381 #define TRBTRG_TRG_SHIFT 0
384 #define TRBIDR_ALIGN_MASK GENMASK(3, 0)
385 #define TRBIDR_ALIGN_SHIFT 0
387 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
388 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
390 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
392 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
393 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
395 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
396 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
397 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
398 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
399 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
401 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
402 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
404 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
405 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
406 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
407 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
408 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
409 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
412 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
413 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
414 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
417 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
418 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
419 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
420 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
421 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
422 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
423 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
424 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
425 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
426 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
427 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
428 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
429 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
430 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
432 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
433 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
435 #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
437 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
439 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
440 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
441 #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
442 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
444 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
446 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
447 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
449 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
450 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
452 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
453 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
454 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
455 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
456 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
457 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
458 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
459 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
460 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
461 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
462 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
463 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
464 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
466 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
467 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
469 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
472 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
473 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
476 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
479 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
480 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
483 * Group 0 of activity monitors (architected):
485 * Counter: 11 011 1101 010:n<3> n<2:0>
486 * Type: 11 011 1101 011:n<3> n<2:0>
487 * n: 0-15
491 * Counter: 11 011 1101 110:n<3> n<2:0>
492 * Type: 11 011 1101 111:n<3> n<2:0>
493 * n: 0-15
496 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
497 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
498 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
499 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
502 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
505 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
507 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
509 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
510 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
511 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
513 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
514 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
516 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
517 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
518 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
520 #define __PMEV_op2(n) ((n) & 0x7)
521 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
522 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
523 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
524 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
526 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
528 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
529 #define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
530 #define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
531 #define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
532 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
533 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
534 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
535 #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4)
536 #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5)
537 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
538 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
539 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
540 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
541 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
542 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
543 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
544 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
545 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
547 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
548 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
549 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
552 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
554 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
555 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
558 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
560 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
561 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
562 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
563 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
564 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
565 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
566 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
567 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
569 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
570 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
573 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
579 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
580 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
583 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
590 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
591 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
592 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
593 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
594 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
595 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
596 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
597 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
598 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
599 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
600 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
601 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
602 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
603 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
604 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
605 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
606 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
607 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
608 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
609 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
610 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
611 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
612 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
613 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
620 #define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT)
621 #define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT)
622 #define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT)
623 #define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT)
636 #define SCTLR_ELx_SA (BIT(3))
639 #define SCTLR_ELx_M (BIT(0))
649 #define ENDIAN_SET_EL2 0
665 #define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
666 #define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
667 #define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
668 #define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
691 #define ENDIAN_SET_EL1 0
705 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
706 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
707 #define MAIR_ATTR_NORMAL_NC UL(0x44)
708 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
709 #define MAIR_ATTR_NORMAL UL(0xff)
710 #define MAIR_ATTR_MASK UL(0xff)
731 #define ID_AA64ISAR0_TLB_RANGE_NI 0x0
732 #define ID_AA64ISAR0_TLB_RANGE 0x2
748 #define ID_AA64ISAR1_DPB_SHIFT 0
750 #define ID_AA64ISAR1_APA_NI 0x0
751 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1
752 #define ID_AA64ISAR1_APA_ARCH_EPAC 0x2
753 #define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3
754 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4
755 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5
756 #define ID_AA64ISAR1_API_NI 0x0
757 #define ID_AA64ISAR1_API_IMP_DEF 0x1
758 #define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2
759 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3
760 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4
761 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5
762 #define ID_AA64ISAR1_GPA_NI 0x0
763 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
764 #define ID_AA64ISAR1_GPI_NI 0x0
765 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1
782 #define ID_AA64PFR0_EL0_SHIFT 0
784 #define ID_AA64PFR0_AMU 0x1
785 #define ID_AA64PFR0_SVE 0x1
786 #define ID_AA64PFR0_RAS_V1 0x1
787 #define ID_AA64PFR0_RAS_V1P1 0x2
788 #define ID_AA64PFR0_FP_NI 0xf
789 #define ID_AA64PFR0_FP_SUPPORTED 0x0
790 #define ID_AA64PFR0_ASIMD_NI 0xf
791 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
792 #define ID_AA64PFR0_ELx_64BIT_ONLY 0x1
793 #define ID_AA64PFR0_ELx_32BIT_64BIT 0x2
800 #define ID_AA64PFR1_BT_SHIFT 0
802 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
805 #define ID_AA64PFR1_BT_BTI 0x1
807 #define ID_AA64PFR1_MTE_NI 0x0
808 #define ID_AA64PFR1_MTE_EL0 0x1
809 #define ID_AA64PFR1_MTE 0x2
820 #define ID_AA64ZFR0_SVEVER_SHIFT 0
822 #define ID_AA64ZFR0_F64MM 0x1
823 #define ID_AA64ZFR0_F32MM 0x1
824 #define ID_AA64ZFR0_I8MM 0x1
825 #define ID_AA64ZFR0_BF16 0x1
826 #define ID_AA64ZFR0_SM4 0x1
827 #define ID_AA64ZFR0_SHA3 0x1
828 #define ID_AA64ZFR0_BITPERM 0x1
829 #define ID_AA64ZFR0_AES 0x1
830 #define ID_AA64ZFR0_AES_PMULL 0x2
831 #define ID_AA64ZFR0_SVEVER_SVE2 0x1
847 #define ID_AA64MMFR0_PARANGE_SHIFT 0
849 #define ID_AA64MMFR0_ASID_8 0x0
850 #define ID_AA64MMFR0_ASID_16 0x2
852 #define ID_AA64MMFR0_TGRAN4_NI 0xf
853 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0
854 #define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7
855 #define ID_AA64MMFR0_TGRAN64_NI 0xf
856 #define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0
857 #define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7
858 #define ID_AA64MMFR0_TGRAN16_NI 0x0
859 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1
860 #define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf
862 #define ID_AA64MMFR0_PARANGE_32 0x0
863 #define ID_AA64MMFR0_PARANGE_36 0x1
864 #define ID_AA64MMFR0_PARANGE_40 0x2
865 #define ID_AA64MMFR0_PARANGE_42 0x3
866 #define ID_AA64MMFR0_PARANGE_44 0x4
867 #define ID_AA64MMFR0_PARANGE_48 0x5
868 #define ID_AA64MMFR0_PARANGE_52 0x6
872 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
873 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1
874 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2
875 #define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7
893 #define ID_AA64MMFR1_HADBS_SHIFT 0
895 #define ID_AA64MMFR1_VMIDBITS_8 0
913 #define ID_AA64MMFR2_CNP_SHIFT 0
926 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
928 #define ID_AA64DFR0_PMUVER_8_0 0x1
929 #define ID_AA64DFR0_PMUVER_8_1 0x4
930 #define ID_AA64DFR0_PMUVER_8_4 0x5
931 #define ID_AA64DFR0_PMUVER_8_5 0x6
932 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf
934 #define ID_AA64DFR0_PMSVER_8_2 0x1
935 #define ID_AA64DFR0_PMSVER_8_3 0x2
939 #define ID_DFR0_PERFMON_8_0 0x3
940 #define ID_DFR0_PERFMON_8_1 0x4
941 #define ID_DFR0_PERFMON_8_4 0x5
942 #define ID_DFR0_PERFMON_8_5 0x6
951 #define ID_ISAR4_UNPRIV_SHIFT 0
953 #define ID_DFR1_MTPMU_SHIFT 0
961 #define ID_ISAR0_SWAP_SHIFT 0
968 #define ID_ISAR5_SEVL_SHIFT 0
976 #define ID_ISAR6_JSCVT_SHIFT 0
985 #define ID_MMFR0_VMSA_SHIFT 0
994 #define ID_MMFR4_SPECSEI_SHIFT 0
996 #define ID_MMFR5_ETS_SHIFT 0
1003 #define ID_PFR0_STATE0_SHIFT 0
1011 #define ID_DFR0_COPDBG_SHIFT 0
1014 #define ID_PFR2_CSV3_SHIFT 0
1023 #define MVFR0_SIMD_SHIFT 0
1032 #define MVFR1_FPFTZ_SHIFT 0
1041 #define ID_PFR1_PROGMOD_SHIFT 0
1061 #define MVFR2_SIMDMISC_SHIFT 0
1064 #define DCZID_BS_SHIFT 0
1071 #define ZCR_ELx_LEN_SHIFT 0
1073 #define ZCR_ELx_LEN_MASK 0x1ff
1085 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL
1088 #define SYS_RGSR_EL1_TAG_MASK 0xfUL
1090 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
1093 #define SYS_GMID_EL1_BS_SHIFT 0
1097 #define SYS_TFSR_EL1_TF0_SHIFT 0
1102 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
1106 #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
1107 #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
1108 #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
1109 #define TRFCR_EL2_CX BIT(3)
1111 #define TRFCR_ELx_E0TRE BIT(0)
1116 #define ICH_MISR_EOI (1 << 0)
1120 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1125 #define ICH_LR_STATE (3ULL << 62)
1129 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
1131 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
1134 #define ICH_HCR_EN (1 << 0)
1136 #define ICH_HCR_NPIE (1 << 3)
1141 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
1146 #define ICH_VMCR_FIQ_EN_SHIFT 3
1157 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
1158 #define ICH_VMCR_ENG0_SHIFT 0
1176 #define ARM64_FEATURE_MASK(x) (GENMASK_ULL(x##_SHIFT + ARM64_FEATURE_FIELD_BITS - 1, x##_SHIFT))
1180 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1186 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
1190 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
1200 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1208 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \
1214 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \
1239 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1251 } while (0)
1259 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1266 } while (0)
1270 * set mask are set. Other bits are left as-is.
1277 } while (0)
1284 } while (0)