Lines Matching full:transmit

84 /* Transmit Buffer for Serializer n */
122  * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
124 #define DITEN	BIT(0)	/* Transmit DIT mode enable/disable */
129  * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
151  * DAVINCI_MCASP_TXFMCTL_REG -  Transmit Frame Control Register Bits
167  * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
185  * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
224  * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
243 #define TXSERCLR	BIT(10)	/* Transmit Serializer Clear */
251 #define XRERR		BIT(8) /* Transmit/Receive error */
252 #define XRDATA		BIT(5) /* Transmit/Receive data ready */
298 /* Source of High-frequency transmit/receive clock */