Lines Matching +full:dai +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
22 #include <sound/soc-dai.h>
85 #define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
93 /* Defines required for sun8i-h3 support */
106 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
119 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
121 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
128 #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
133 /* Defines required for sun50i-h6 support */
137 #define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
139 #define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
157 * struct sun4i_i2s_quirks - Differences between SoC variants.
200 * @slots: channels per frame + padding slots, regardless of format
204 unsigned int channels, unsigned int slots,
243 /* TODO - extend divide ratio supported by newer SoCs */
255 /* TODO - extend divide ratio supported by newer SoCs */
278 return i2s->mclk_freq; in sun4i_i2s_get_bclk_parent_rate()
283 return clk_get_rate(i2s->mod_clk); in sun8i_i2s_get_bclk_parent_rate()
289 unsigned int channels, in sun4i_i2s_get_bclk_div() argument
292 const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers; in sun4i_i2s_get_bclk_div()
293 int div = parent_rate / sampling_rate / word_size / channels; in sun4i_i2s_get_bclk_div()
296 for (i = 0; i < i2s->variant->num_bclk_dividers; i++) { in sun4i_i2s_get_bclk_div()
299 if (bdiv->div == div) in sun4i_i2s_get_bclk_div()
300 return bdiv->val; in sun4i_i2s_get_bclk_div()
303 return -EINVAL; in sun4i_i2s_get_bclk_div()
310 const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers; in sun4i_i2s_get_mclk_div()
314 for (i = 0; i < i2s->variant->num_mclk_dividers; i++) { in sun4i_i2s_get_mclk_div()
317 if (mdiv->div == div) in sun4i_i2s_get_mclk_div()
318 return mdiv->val; in sun4i_i2s_get_mclk_div()
321 return -EINVAL; in sun4i_i2s_get_mclk_div()
336 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, in sun4i_i2s_set_clk_rate() argument
341 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_set_clk_rate()
369 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); in sun4i_i2s_set_clk_rate()
370 return -EINVAL; in sun4i_i2s_set_clk_rate()
373 ret = clk_set_rate(i2s->mod_clk, clk_rate); in sun4i_i2s_set_clk_rate()
377 oversample_rate = i2s->mclk_freq / rate; in sun4i_i2s_set_clk_rate()
379 dev_err(dai->dev, "Unsupported oversample rate: %d\n", in sun4i_i2s_set_clk_rate()
381 return -EINVAL; in sun4i_i2s_set_clk_rate()
384 bclk_parent_rate = i2s->variant->get_bclk_parent_rate(i2s); in sun4i_i2s_set_clk_rate()
388 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); in sun4i_i2s_set_clk_rate()
389 return -EINVAL; in sun4i_i2s_set_clk_rate()
392 mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq); in sun4i_i2s_set_clk_rate()
394 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); in sun4i_i2s_set_clk_rate()
395 return -EINVAL; in sun4i_i2s_set_clk_rate()
398 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, in sun4i_i2s_set_clk_rate()
402 regmap_field_write(i2s->field_clkdiv_mclk_en, 1); in sun4i_i2s_set_clk_rate()
418 return -EINVAL; in sun4i_i2s_get_sr()
434 return -EINVAL; in sun4i_i2s_get_wss()
456 return -EINVAL; in sun8i_i2s_get_sr_wss()
460 unsigned int channels, unsigned int slots, in sun4i_i2s_set_chan_cfg() argument
463 /* Map the channels for playback and capture */ in sun4i_i2s_set_chan_cfg()
464 regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun4i_i2s_set_chan_cfg()
465 regmap_write(i2s->regmap, SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210); in sun4i_i2s_set_chan_cfg()
467 /* Configure the channels */ in sun4i_i2s_set_chan_cfg()
468 regmap_update_bits(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
470 SUN4I_I2S_CHAN_SEL(channels)); in sun4i_i2s_set_chan_cfg()
471 regmap_update_bits(i2s->regmap, SUN4I_I2S_RX_CHAN_SEL_REG, in sun4i_i2s_set_chan_cfg()
473 SUN4I_I2S_CHAN_SEL(channels)); in sun4i_i2s_set_chan_cfg()
479 unsigned int channels, unsigned int slots, in sun8i_i2s_set_chan_cfg() argument
484 /* Map the channels for playback and capture */ in sun8i_i2s_set_chan_cfg()
485 regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
486 regmap_write(i2s->regmap, SUN8I_I2S_RX_CHAN_MAP_REG, 0x76543210); in sun8i_i2s_set_chan_cfg()
488 /* Configure the channels */ in sun8i_i2s_set_chan_cfg()
489 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
491 SUN4I_I2S_CHAN_SEL(channels)); in sun8i_i2s_set_chan_cfg()
492 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
494 SUN4I_I2S_CHAN_SEL(channels)); in sun8i_i2s_set_chan_cfg()
496 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
498 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); in sun8i_i2s_set_chan_cfg()
499 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun8i_i2s_set_chan_cfg()
501 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); in sun8i_i2s_set_chan_cfg()
503 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun8i_i2s_set_chan_cfg()
516 return -EINVAL; in sun8i_i2s_set_chan_cfg()
519 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_chan_cfg()
523 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_chan_cfg()
525 SUN8I_I2S_TX_CHAN_EN(channels)); in sun8i_i2s_set_chan_cfg()
531 unsigned int channels, unsigned int slots, in sun50i_h6_i2s_set_chan_cfg() argument
536 /* Map the channels for playback and capture */ in sun50i_h6_i2s_set_chan_cfg()
537 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG(0), 0xFEDCBA98); in sun50i_h6_i2s_set_chan_cfg()
538 regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG(0), 0x76543210); in sun50i_h6_i2s_set_chan_cfg()
539 if (i2s->variant->num_din_pins > 1) { in sun50i_h6_i2s_set_chan_cfg()
540 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP0_REG, 0x0F0E0D0C); in sun50i_h6_i2s_set_chan_cfg()
541 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP1_REG, 0x0B0A0908); in sun50i_h6_i2s_set_chan_cfg()
542 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP2_REG, 0x07060504); in sun50i_h6_i2s_set_chan_cfg()
543 regmap_write(i2s->regmap, SUN50I_R329_I2S_RX_CHAN_MAP3_REG, 0x03020100); in sun50i_h6_i2s_set_chan_cfg()
545 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98); in sun50i_h6_i2s_set_chan_cfg()
546 regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210); in sun50i_h6_i2s_set_chan_cfg()
549 /* Configure the channels */ in sun50i_h6_i2s_set_chan_cfg()
550 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), in sun50i_h6_i2s_set_chan_cfg()
552 SUN50I_H6_I2S_TX_CHAN_SEL(channels)); in sun50i_h6_i2s_set_chan_cfg()
553 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, in sun50i_h6_i2s_set_chan_cfg()
555 SUN50I_H6_I2S_TX_CHAN_SEL(channels)); in sun50i_h6_i2s_set_chan_cfg()
557 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun50i_h6_i2s_set_chan_cfg()
559 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); in sun50i_h6_i2s_set_chan_cfg()
560 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, in sun50i_h6_i2s_set_chan_cfg()
562 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); in sun50i_h6_i2s_set_chan_cfg()
564 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) { in sun50i_h6_i2s_set_chan_cfg()
577 return -EINVAL; in sun50i_h6_i2s_set_chan_cfg()
580 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun50i_h6_i2s_set_chan_cfg()
584 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_SEL_REG(0), in sun50i_h6_i2s_set_chan_cfg()
586 SUN50I_H6_I2S_TX_CHAN_EN(channels)); in sun50i_h6_i2s_set_chan_cfg()
593 struct snd_soc_dai *dai) in sun4i_i2s_hw_params() argument
595 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_hw_params()
598 unsigned int channels = params_channels(params); in sun4i_i2s_hw_params() local
600 unsigned int slots = channels; in sun4i_i2s_hw_params()
605 if (i2s->slots) in sun4i_i2s_hw_params()
606 slots = i2s->slots; in sun4i_i2s_hw_params()
608 if (i2s->slot_width) in sun4i_i2s_hw_params()
609 slot_width = i2s->slot_width; in sun4i_i2s_hw_params()
611 ret = i2s->variant->set_chan_cfg(i2s, channels, slots, slot_width); in sun4i_i2s_hw_params()
613 dev_err(dai->dev, "Invalid channel configuration\n"); in sun4i_i2s_hw_params()
618 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_hw_params()
632 dev_err(dai->dev, "Unsupported physical sample width: %d\n", in sun4i_i2s_hw_params()
634 return -EINVAL; in sun4i_i2s_hw_params()
636 i2s->playback_dma_data.addr_width = width; in sun4i_i2s_hw_params()
638 sr = i2s->variant->get_sr(word_size); in sun4i_i2s_hw_params()
640 return -EINVAL; in sun4i_i2s_hw_params()
642 wss = i2s->variant->get_wss(slot_width); in sun4i_i2s_hw_params()
644 return -EINVAL; in sun4i_i2s_hw_params()
646 regmap_field_write(i2s->field_fmt_wss, wss); in sun4i_i2s_hw_params()
647 regmap_field_write(i2s->field_fmt_sr, sr); in sun4i_i2s_hw_params()
649 return sun4i_i2s_set_clk_rate(dai, params_rate(params), in sun4i_i2s_hw_params()
658 /* DAI clock polarity */ in sun4i_i2s_set_soc_fmt()
677 return -EINVAL; in sun4i_i2s_set_soc_fmt()
680 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
685 /* DAI Mode */ in sun4i_i2s_set_soc_fmt()
700 return -EINVAL; in sun4i_i2s_set_soc_fmt()
703 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_soc_fmt()
706 /* DAI clock master masks */ in sun4i_i2s_set_soc_fmt()
719 return -EINVAL; in sun4i_i2s_set_soc_fmt()
721 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_set_soc_fmt()
734 * DAI clock polarity in sun8i_i2s_set_soc_fmt()
758 return -EINVAL; in sun8i_i2s_set_soc_fmt()
761 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun8i_i2s_set_soc_fmt()
766 /* DAI Mode */ in sun8i_i2s_set_soc_fmt()
794 return -EINVAL; in sun8i_i2s_set_soc_fmt()
797 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
799 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
802 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, in sun8i_i2s_set_soc_fmt()
806 /* DAI clock master masks */ in sun8i_i2s_set_soc_fmt()
819 return -EINVAL; in sun8i_i2s_set_soc_fmt()
822 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun8i_i2s_set_soc_fmt()
827 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, in sun8i_i2s_set_soc_fmt()
841 * DAI clock polarity in sun50i_h6_i2s_set_soc_fmt()
865 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
868 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun50i_h6_i2s_set_soc_fmt()
873 /* DAI Mode */ in sun50i_h6_i2s_set_soc_fmt()
901 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
904 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun50i_h6_i2s_set_soc_fmt()
906 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, in sun50i_h6_i2s_set_soc_fmt()
909 regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG, in sun50i_h6_i2s_set_soc_fmt()
913 /* DAI clock master masks */ in sun50i_h6_i2s_set_soc_fmt()
926 return -EINVAL; in sun50i_h6_i2s_set_soc_fmt()
929 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun50i_h6_i2s_set_soc_fmt()
934 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT1_REG, in sun50i_h6_i2s_set_soc_fmt()
941 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) in sun4i_i2s_set_fmt() argument
943 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_set_fmt()
946 ret = i2s->variant->set_fmt(i2s, fmt); in sun4i_i2s_set_fmt()
948 dev_err(dai->dev, "Unsupported format configuration\n"); in sun4i_i2s_set_fmt()
952 i2s->format = fmt; in sun4i_i2s_set_fmt()
960 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_capture()
965 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); in sun4i_i2s_start_capture()
968 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_capture()
973 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_capture()
981 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, in sun4i_i2s_start_playback()
986 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); in sun4i_i2s_start_playback()
989 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_start_playback()
994 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_start_playback()
1002 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_capture()
1007 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_capture()
1015 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_stop_playback()
1020 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, in sun4i_i2s_stop_playback()
1026 struct snd_soc_dai *dai) in sun4i_i2s_trigger() argument
1028 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_trigger()
1034 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
1043 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in sun4i_i2s_trigger()
1050 return -EINVAL; in sun4i_i2s_trigger()
1056 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, in sun4i_i2s_set_sysclk() argument
1059 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_set_sysclk()
1062 return -EINVAL; in sun4i_i2s_set_sysclk()
1064 i2s->mclk_freq = freq; in sun4i_i2s_set_sysclk()
1069 static int sun4i_i2s_set_tdm_slot(struct snd_soc_dai *dai, in sun4i_i2s_set_tdm_slot() argument
1073 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_set_tdm_slot()
1076 return -EINVAL; in sun4i_i2s_set_tdm_slot()
1078 i2s->slots = slots; in sun4i_i2s_set_tdm_slot()
1079 i2s->slot_width = slot_width; in sun4i_i2s_set_tdm_slot()
1092 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) in sun4i_i2s_dai_probe() argument
1094 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); in sun4i_i2s_dai_probe()
1096 snd_soc_dai_init_dma_data(dai, in sun4i_i2s_dai_probe()
1097 &i2s->playback_dma_data, in sun4i_i2s_dai_probe()
1098 &i2s->capture_dma_data); in sun4i_i2s_dai_probe()
1128 .name = "sun4i-dai",
1285 ret = clk_prepare_enable(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1291 regcache_cache_only(i2s->regmap, false); in sun4i_i2s_runtime_resume()
1292 regcache_mark_dirty(i2s->regmap); in sun4i_i2s_runtime_resume()
1294 ret = regcache_sync(i2s->regmap); in sun4i_i2s_runtime_resume()
1301 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1305 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_resume()
1309 ret = clk_prepare_enable(i2s->mod_clk); in sun4i_i2s_runtime_resume()
1318 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_resume()
1326 clk_disable_unprepare(i2s->mod_clk); in sun4i_i2s_runtime_suspend()
1329 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1333 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, in sun4i_i2s_runtime_suspend()
1336 regcache_cache_only(i2s->regmap, true); in sun4i_i2s_runtime_suspend()
1338 clk_disable_unprepare(i2s->bus_clk); in sun4i_i2s_runtime_suspend()
1479 i2s->field_clkdiv_mclk_en = in sun4i_i2s_init_regmap_fields()
1480 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1481 i2s->variant->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1482 if (IS_ERR(i2s->field_clkdiv_mclk_en)) in sun4i_i2s_init_regmap_fields()
1483 return PTR_ERR(i2s->field_clkdiv_mclk_en); in sun4i_i2s_init_regmap_fields()
1485 i2s->field_fmt_wss = in sun4i_i2s_init_regmap_fields()
1486 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1487 i2s->variant->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1488 if (IS_ERR(i2s->field_fmt_wss)) in sun4i_i2s_init_regmap_fields()
1489 return PTR_ERR(i2s->field_fmt_wss); in sun4i_i2s_init_regmap_fields()
1491 i2s->field_fmt_sr = in sun4i_i2s_init_regmap_fields()
1492 devm_regmap_field_alloc(dev, i2s->regmap, in sun4i_i2s_init_regmap_fields()
1493 i2s->variant->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1494 if (IS_ERR(i2s->field_fmt_sr)) in sun4i_i2s_init_regmap_fields()
1495 return PTR_ERR(i2s->field_fmt_sr); in sun4i_i2s_init_regmap_fields()
1507 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); in sun4i_i2s_probe()
1509 return -ENOMEM; in sun4i_i2s_probe()
1520 i2s->variant = of_device_get_match_data(&pdev->dev); in sun4i_i2s_probe()
1521 if (!i2s->variant) { in sun4i_i2s_probe()
1522 dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); in sun4i_i2s_probe()
1523 return -ENODEV; in sun4i_i2s_probe()
1526 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb"); in sun4i_i2s_probe()
1527 if (IS_ERR(i2s->bus_clk)) { in sun4i_i2s_probe()
1528 dev_err(&pdev->dev, "Can't get our bus clock\n"); in sun4i_i2s_probe()
1529 return PTR_ERR(i2s->bus_clk); in sun4i_i2s_probe()
1532 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, in sun4i_i2s_probe()
1533 i2s->variant->sun4i_i2s_regmap); in sun4i_i2s_probe()
1534 if (IS_ERR(i2s->regmap)) { in sun4i_i2s_probe()
1535 dev_err(&pdev->dev, "Regmap initialisation failed\n"); in sun4i_i2s_probe()
1536 return PTR_ERR(i2s->regmap); in sun4i_i2s_probe()
1539 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod"); in sun4i_i2s_probe()
1540 if (IS_ERR(i2s->mod_clk)) { in sun4i_i2s_probe()
1541 dev_err(&pdev->dev, "Can't get our mod clock\n"); in sun4i_i2s_probe()
1542 return PTR_ERR(i2s->mod_clk); in sun4i_i2s_probe()
1545 if (i2s->variant->has_reset) { in sun4i_i2s_probe()
1546 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun4i_i2s_probe()
1547 if (IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1548 dev_err(&pdev->dev, "Failed to get reset control\n"); in sun4i_i2s_probe()
1549 return PTR_ERR(i2s->rst); in sun4i_i2s_probe()
1553 if (!IS_ERR(i2s->rst)) { in sun4i_i2s_probe()
1554 ret = reset_control_deassert(i2s->rst); in sun4i_i2s_probe()
1556 dev_err(&pdev->dev, in sun4i_i2s_probe()
1558 return -EINVAL; in sun4i_i2s_probe()
1562 i2s->playback_dma_data.addr = res->start + in sun4i_i2s_probe()
1563 i2s->variant->reg_offset_txdata; in sun4i_i2s_probe()
1564 i2s->playback_dma_data.maxburst = 8; in sun4i_i2s_probe()
1566 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; in sun4i_i2s_probe()
1567 i2s->capture_dma_data.maxburst = 8; in sun4i_i2s_probe()
1569 pm_runtime_enable(&pdev->dev); in sun4i_i2s_probe()
1570 if (!pm_runtime_enabled(&pdev->dev)) { in sun4i_i2s_probe()
1571 ret = sun4i_i2s_runtime_resume(&pdev->dev); in sun4i_i2s_probe()
1576 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s); in sun4i_i2s_probe()
1578 dev_err(&pdev->dev, "Could not initialise regmap fields\n"); in sun4i_i2s_probe()
1582 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in sun4i_i2s_probe()
1584 dev_err(&pdev->dev, "Could not register PCM\n"); in sun4i_i2s_probe()
1588 ret = devm_snd_soc_register_component(&pdev->dev, in sun4i_i2s_probe()
1592 dev_err(&pdev->dev, "Could not register DAI\n"); in sun4i_i2s_probe()
1599 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_probe()
1600 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_probe()
1602 pm_runtime_disable(&pdev->dev); in sun4i_i2s_probe()
1603 if (!IS_ERR(i2s->rst)) in sun4i_i2s_probe()
1604 reset_control_assert(i2s->rst); in sun4i_i2s_probe()
1611 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev); in sun4i_i2s_remove()
1613 pm_runtime_disable(&pdev->dev); in sun4i_i2s_remove()
1614 if (!pm_runtime_status_suspended(&pdev->dev)) in sun4i_i2s_remove()
1615 sun4i_i2s_runtime_suspend(&pdev->dev); in sun4i_i2s_remove()
1617 if (!IS_ERR(i2s->rst)) in sun4i_i2s_remove()
1618 reset_control_assert(i2s->rst); in sun4i_i2s_remove()
1625 .compatible = "allwinner,sun4i-a10-i2s",
1629 .compatible = "allwinner,sun6i-a31-i2s",
1633 .compatible = "allwinner,sun8i-a83t-i2s",
1637 .compatible = "allwinner,sun8i-h3-i2s",
1641 .compatible = "allwinner,sun50i-a64-codec-i2s",
1645 .compatible = "allwinner,sun50i-h6-i2s",
1649 .compatible = "allwinner,sun50i-r329-i2s",
1665 .name = "sun4i-i2s",
1673 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");