Lines Matching refs:snd_sof_dsp_read
81 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_ERROR_STATUS); in config_dma_channel()
82 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32)); in config_dma_channel()
228 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); in configure_and_run_sha_dma()
258 fw_qualifier = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER); in configure_and_run_sha_dma()
273 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); in acp_dma_status()
291 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); in memcpy_from_scratch()
322 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); in acp_irq_thread()
329 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); in acp_irq_thread()
331 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset)) { in acp_irq_thread()
360 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); in acp_irq_handler()
374 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); in acp_power_on()