1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
20  * capture frontend DAI. The logic behind this two types of fifo is very
48 	struct snd_soc_pcm_runtime *rtd = ss->private_data;  in axg_fifo_dai()
64 	return dai->dev;  in axg_fifo_dev()
67 static void __dma_enable(struct axg_fifo *fifo,  bool enable)  in __dma_enable()  argument
69 	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,  in __dma_enable()
76 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_trigger()  local
82 		__dma_enable(fifo, true);  in axg_fifo_pcm_trigger()
87 		__dma_enable(fifo, false);  in axg_fifo_pcm_trigger()
90 		return -EINVAL;  in axg_fifo_pcm_trigger()
100 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_pointer()  local
101 	struct snd_pcm_runtime *runtime = ss->runtime;  in axg_fifo_pcm_pointer()
104 	regmap_read(fifo->map, FIFO_STATUS2, &addr);  in axg_fifo_pcm_pointer()
106 	return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr);  in axg_fifo_pcm_pointer()
114 	struct snd_pcm_runtime *runtime = ss->runtime;  in axg_fifo_pcm_hw_params()
115 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_hw_params()  local
122 	end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST;  in axg_fifo_pcm_hw_params()
123 	regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);  in axg_fifo_pcm_hw_params()
124 	regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);  in axg_fifo_pcm_hw_params()
128 	regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);  in axg_fifo_pcm_hw_params()
131 	 * Start the fifo request on the smallest of the following:  in axg_fifo_pcm_hw_params()
132 	 * - Half the fifo size  in axg_fifo_pcm_hw_params()
133 	 * - Half the period size  in axg_fifo_pcm_hw_params()
135 	threshold = min(period / 2, fifo->depth / 2);  in axg_fifo_pcm_hw_params()
139 	 * V = (threshold / burst) - 1  in axg_fifo_pcm_hw_params()
142 	regmap_field_write(fifo->field_threshold,  in axg_fifo_pcm_hw_params()
143 			   threshold ? threshold - 1 : 0);  in axg_fifo_pcm_hw_params()
146 	irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT;  in axg_fifo_pcm_hw_params()
147 	regmap_update_bits(fifo->map, FIFO_CTRL0,  in axg_fifo_pcm_hw_params()
159 	struct axg_fifo *fifo = axg_fifo_data(ss);  in g12a_fifo_pcm_hw_params()  local
160 	struct snd_pcm_runtime *runtime = ss->runtime;  in g12a_fifo_pcm_hw_params()
168 	regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);  in g12a_fifo_pcm_hw_params()
177 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_hw_free()  local
180 	regmap_update_bits(fifo->map, FIFO_CTRL0,  in axg_fifo_pcm_hw_free()
187 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)  in axg_fifo_ack_irq()  argument
189 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in axg_fifo_ack_irq()
194 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in axg_fifo_ack_irq()
202 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_irq_block()  local
205 	regmap_read(fifo->map, FIFO_STATUS1, &status);  in axg_fifo_pcm_irq_block()
211 		dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n",  in axg_fifo_pcm_irq_block()
215 	axg_fifo_ack_irq(fifo, status);  in axg_fifo_pcm_irq_block()
223 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_open()  local
230 	 * Make sure the buffer and period size are multiple of the FIFO  in axg_fifo_pcm_open()
233 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,  in axg_fifo_pcm_open()
239 	ret = snd_pcm_hw_constraint_step(ss->runtime, 0,  in axg_fifo_pcm_open()
245 	ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,  in axg_fifo_pcm_open()
250 	/* Enable pclk to access registers and clock the fifo ip */  in axg_fifo_pcm_open()
251 	ret = clk_prepare_enable(fifo->pclk);  in axg_fifo_pcm_open()
256 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in axg_fifo_pcm_open()
261 	__dma_enable(fifo, false);  in axg_fifo_pcm_open()
264 	regmap_update_bits(fifo->map, FIFO_CTRL0,  in axg_fifo_pcm_open()
268 	axg_fifo_ack_irq(fifo, FIFO_INT_MASK);  in axg_fifo_pcm_open()
271 	ret = reset_control_deassert(fifo->arb);  in axg_fifo_pcm_open()
278 	clk_disable_unprepare(fifo->pclk);  in axg_fifo_pcm_open()
280 	free_irq(fifo->irq, ss);  in axg_fifo_pcm_open()
288 	struct axg_fifo *fifo = axg_fifo_data(ss);  in axg_fifo_pcm_close()  local
292 	ret = reset_control_assert(fifo->arb);  in axg_fifo_pcm_close()
294 	/* Disable fifo ip and register access */  in axg_fifo_pcm_close()
295 	clk_disable_unprepare(fifo->pclk);  in axg_fifo_pcm_close()
298 	free_irq(fifo->irq, ss);  in axg_fifo_pcm_close()
306 	struct snd_card *card = rtd->card->snd_card;  in axg_fifo_pcm_new()
307 	size_t size = axg_fifo_hw.buffer_bytes_max;  in axg_fifo_pcm_new()  local
309 	snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream,  in axg_fifo_pcm_new()
310 				   SNDRV_DMA_TYPE_DEV, card->dev,  in axg_fifo_pcm_new()
311 				   size, size);  in axg_fifo_pcm_new()
325 	struct device *dev = &pdev->dev;  in axg_fifo_probe()
327 	struct axg_fifo *fifo;  in axg_fifo_probe()  local
334 		return -ENODEV;  in axg_fifo_probe()
337 	fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);  in axg_fifo_probe()
338 	if (!fifo)  in axg_fifo_probe()
339 		return -ENOMEM;  in axg_fifo_probe()
340 	platform_set_drvdata(pdev, fifo);  in axg_fifo_probe()
346 	fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);  in axg_fifo_probe()
347 	if (IS_ERR(fifo->map)) {  in axg_fifo_probe()
349 			PTR_ERR(fifo->map));  in axg_fifo_probe()
350 		return PTR_ERR(fifo->map);  in axg_fifo_probe()
353 	fifo->pclk = devm_clk_get(dev, NULL);  in axg_fifo_probe()
354 	if (IS_ERR(fifo->pclk))  in axg_fifo_probe()
355 		return dev_err_probe(dev, PTR_ERR(fifo->pclk), "failed to get pclk\n");  in axg_fifo_probe()
357 	fifo->arb = devm_reset_control_get_exclusive(dev, NULL);  in axg_fifo_probe()
358 	if (IS_ERR(fifo->arb))  in axg_fifo_probe()
359 		return dev_err_probe(dev, PTR_ERR(fifo->arb), "failed to get arb reset\n");  in axg_fifo_probe()
361 	fifo->irq = of_irq_get(dev->of_node, 0);  in axg_fifo_probe()
362 	if (fifo->irq <= 0) {  in axg_fifo_probe()
363 		dev_err(dev, "failed to get irq: %d\n", fifo->irq);  in axg_fifo_probe()
364 		return fifo->irq;  in axg_fifo_probe()
367 	fifo->field_threshold =  in axg_fifo_probe()
368 		devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);  in axg_fifo_probe()
369 	if (IS_ERR(fifo->field_threshold))  in axg_fifo_probe()
370 		return PTR_ERR(fifo->field_threshold);  in axg_fifo_probe()
372 	ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",  in axg_fifo_probe()
373 				   &fifo->depth);  in axg_fifo_probe()
376 		if (ret != -EINVAL)  in axg_fifo_probe()
380 		 * DT. In such case, assume the smallest known fifo depth  in axg_fifo_probe()
382 		fifo->depth = 256;  in axg_fifo_probe()
383 		dev_warn(dev, "fifo depth not found, assume %u bytes\n",  in axg_fifo_probe()
384 			 fifo->depth);  in axg_fifo_probe()
387 	return devm_snd_soc_register_component(dev, data->component_drv,  in axg_fifo_probe()
388 					       data->dai_drv, 1);  in axg_fifo_probe()
392 MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");