1 // SPDX-License-Identifier: GPL-2.0
3 // mt8192-afe-clk.c  --  Mediatek 8192 afe clock ctrl
9 #include <linux/arm-smccc.h>
14 #include "mt8192-afe-clk.h"
15 #include "mt8192-afe-common.h"
66 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_set_audio_int_bus_parent()
69 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],  in mt8192_set_audio_int_bus_parent()
70 			     afe_priv->clk[clk_id]);  in mt8192_set_audio_int_bus_parent()
72 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_set_audio_int_bus_parent()
82 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in apll1_mux_setting()
86 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);  in apll1_mux_setting()
88 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll1_mux_setting()
92 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],  in apll1_mux_setting()
93 				     afe_priv->clk[CLK_TOP_APLL1_CK]);  in apll1_mux_setting()
95 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
102 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);  in apll1_mux_setting()
104 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll1_mux_setting()
108 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],  in apll1_mux_setting()
109 				     afe_priv->clk[CLK_TOP_APLL1_D4]);  in apll1_mux_setting()
111 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
117 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],  in apll1_mux_setting()
118 				     afe_priv->clk[CLK_CLK26M]);  in apll1_mux_setting()
120 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
125 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);  in apll1_mux_setting()
127 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],  in apll1_mux_setting()
128 				     afe_priv->clk[CLK_CLK26M]);  in apll1_mux_setting()
130 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
135 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);  in apll1_mux_setting()
144 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in apll2_mux_setting()
148 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);  in apll2_mux_setting()
150 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll2_mux_setting()
154 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],  in apll2_mux_setting()
155 				     afe_priv->clk[CLK_TOP_APLL2_CK]);  in apll2_mux_setting()
157 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
164 		ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);  in apll2_mux_setting()
166 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll2_mux_setting()
170 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],  in apll2_mux_setting()
171 				     afe_priv->clk[CLK_TOP_APLL2_D4]);  in apll2_mux_setting()
173 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
179 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],  in apll2_mux_setting()
180 				     afe_priv->clk[CLK_CLK26M]);  in apll2_mux_setting()
182 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
187 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);  in apll2_mux_setting()
189 		ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],  in apll2_mux_setting()
190 				     afe_priv->clk[CLK_CLK26M]);  in apll2_mux_setting()
192 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
197 		clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);  in apll2_mux_setting()
206 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_afe_enable_clock()
209 	dev_info(afe->dev, "%s()\n", __func__);  in mt8192_afe_enable_clock()
211 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);  in mt8192_afe_enable_clock()
213 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
218 	ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_AUDIO_26M]);  in mt8192_afe_enable_clock()
220 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
225 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);  in mt8192_afe_enable_clock()
227 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
231 	ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],  in mt8192_afe_enable_clock()
232 			     afe_priv->clk[CLK_CLK26M]);  in mt8192_afe_enable_clock()
234 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_afe_enable_clock()
240 	ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);  in mt8192_afe_enable_clock()
242 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
249 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_afe_enable_clock()
255 	ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUDIO_H],  in mt8192_afe_enable_clock()
256 			     afe_priv->clk[CLK_TOP_APLL2_CK]);  in mt8192_afe_enable_clock()
258 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8192_afe_enable_clock()
264 	ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);  in mt8192_afe_enable_clock()
266 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_afe_enable_clock()
277 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_afe_disable_clock()
279 	dev_info(afe->dev, "%s()\n", __func__);  in mt8192_afe_disable_clock()
281 	clk_disable_unprepare(afe_priv->clk[CLK_AFE]);  in mt8192_afe_disable_clock()
283 	clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);  in mt8192_afe_disable_clock()
284 	clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);  in mt8192_afe_disable_clock()
285 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_AUDIO_26M]);  in mt8192_afe_disable_clock()
286 	clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);  in mt8192_afe_disable_clock()
291 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll1_enable()
297 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);  in mt8192_apll1_enable()
299 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll1_enable()
304 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);  in mt8192_apll1_enable()
306 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll1_enable()
311 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,  in mt8192_apll1_enable()
313 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);  in mt8192_apll1_enable()
315 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll1_enable()
325 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll1_disable()
327 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll1_disable()
331 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);  in mt8192_apll1_disable()
333 	clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);  in mt8192_apll1_disable()
334 	clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);  in mt8192_apll1_disable()
341 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll2_enable()
347 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);  in mt8192_apll2_enable()
349 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll2_enable()
354 	ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);  in mt8192_apll2_enable()
356 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8192_apll2_enable()
361 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,  in mt8192_apll2_enable()
363 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);  in mt8192_apll2_enable()
365 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll2_enable()
375 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_apll2_disable()
377 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8192_apll2_disable()
381 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);  in mt8192_apll2_disable()
383 	clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);  in mt8192_apll2_disable()
384 	clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);  in mt8192_apll2_disable()
490 		.m_sel_id = -1,
568 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_mck_enable()
578 		ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);  in mt8192_mck_enable()
580 			dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",  in mt8192_mck_enable()
584 		ret = clk_set_parent(afe_priv->clk[m_sel_id],  in mt8192_mck_enable()
585 				     afe_priv->clk[apll_clk_id]);  in mt8192_mck_enable()
587 			dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",  in mt8192_mck_enable()
595 	ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);  in mt8192_mck_enable()
597 		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",  in mt8192_mck_enable()
601 	ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);  in mt8192_mck_enable()
603 		dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",  in mt8192_mck_enable()
614 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_mck_disable()
618 	clk_disable_unprepare(afe_priv->clk[div_clk_id]);  in mt8192_mck_disable()
620 		clk_disable_unprepare(afe_priv->clk[m_sel_id]);  in mt8192_mck_disable()
625 	struct mt8192_afe_private *afe_priv = afe->platform_priv;  in mt8192_init_clock()
626 	struct device_node *of_node = afe->dev->of_node;  in mt8192_init_clock()
629 	afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),  in mt8192_init_clock()
631 	if (!afe_priv->clk)  in mt8192_init_clock()
632 		return -ENOMEM;  in mt8192_init_clock()
635 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8192_init_clock()
636 		if (IS_ERR(afe_priv->clk[i])) {  in mt8192_init_clock()
637 			dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",  in mt8192_init_clock()
639 				 aud_clks[i], PTR_ERR(afe_priv->clk[i]));  in mt8192_init_clock()
640 			afe_priv->clk[i] = NULL;  in mt8192_init_clock()
644 	afe_priv->apmixedsys = syscon_regmap_lookup_by_phandle(of_node,  in mt8192_init_clock()
645 							       "mediatek,apmixedsys");  in mt8192_init_clock()
646 	if (IS_ERR(afe_priv->apmixedsys)) {  in mt8192_init_clock()
647 		dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",  in mt8192_init_clock()
648 			__func__, PTR_ERR(afe_priv->apmixedsys));  in mt8192_init_clock()
649 		return PTR_ERR(afe_priv->apmixedsys);  in mt8192_init_clock()
652 	afe_priv->topckgen = syscon_regmap_lookup_by_phandle(of_node,  in mt8192_init_clock()
654 	if (IS_ERR(afe_priv->topckgen)) {  in mt8192_init_clock()
655 		dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",  in mt8192_init_clock()
656 			__func__, PTR_ERR(afe_priv->topckgen));  in mt8192_init_clock()
657 		return PTR_ERR(afe_priv->topckgen);  in mt8192_init_clock()
660 	afe_priv->infracfg = syscon_regmap_lookup_by_phandle(of_node,  in mt8192_init_clock()
662 	if (IS_ERR(afe_priv->infracfg)) {  in mt8192_init_clock()
663 		dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",  in mt8192_init_clock()
664 			__func__, PTR_ERR(afe_priv->infracfg));  in mt8192_init_clock()
665 		return PTR_ERR(afe_priv->infracfg);  in mt8192_init_clock()