Lines Matching full:afe
3 // mt8192-afe-clk.c -- Mediatek 8192 afe clock ctrl
14 #include "mt8192-afe-clk.h"
15 #include "mt8192-afe-common.h"
63 int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe, in mt8192_set_audio_int_bus_parent() argument
66 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_set_audio_int_bus_parent()
72 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8192_set_audio_int_bus_parent()
80 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable) in apll1_mux_setting() argument
82 struct mt8192_afe_private *afe_priv = afe->platform_priv; in apll1_mux_setting()
88 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll1_mux_setting()
95 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
104 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll1_mux_setting()
111 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
120 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
130 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll1_mux_setting()
142 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable) in apll2_mux_setting() argument
144 struct mt8192_afe_private *afe_priv = afe->platform_priv; in apll2_mux_setting()
150 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll2_mux_setting()
157 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
166 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in apll2_mux_setting()
173 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
182 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
192 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in apll2_mux_setting()
204 int mt8192_afe_enable_clock(struct mtk_base_afe *afe) in mt8192_afe_enable_clock() argument
206 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_afe_enable_clock()
209 dev_info(afe->dev, "%s()\n", __func__); in mt8192_afe_enable_clock()
213 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_afe_enable_clock()
220 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_afe_enable_clock()
227 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_afe_enable_clock()
234 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8192_afe_enable_clock()
242 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_afe_enable_clock()
247 ret = mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M); in mt8192_afe_enable_clock()
249 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8192_afe_enable_clock()
258 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", in mt8192_afe_enable_clock()
266 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_afe_enable_clock()
275 void mt8192_afe_disable_clock(struct mtk_base_afe *afe) in mt8192_afe_disable_clock() argument
277 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_afe_disable_clock()
279 dev_info(afe->dev, "%s()\n", __func__); in mt8192_afe_disable_clock()
282 mt8192_set_audio_int_bus_parent(afe, CLK_CLK26M); in mt8192_afe_disable_clock()
289 int mt8192_apll1_enable(struct mtk_base_afe *afe) in mt8192_apll1_enable() argument
291 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_apll1_enable()
295 apll1_mux_setting(afe, true); in mt8192_apll1_enable()
299 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_apll1_enable()
306 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_apll1_enable()
311 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, in mt8192_apll1_enable()
313 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1); in mt8192_apll1_enable()
315 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8192_apll1_enable()
323 void mt8192_apll1_disable(struct mtk_base_afe *afe) in mt8192_apll1_disable() argument
325 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_apll1_disable()
327 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8192_apll1_disable()
331 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0); in mt8192_apll1_disable()
336 apll1_mux_setting(afe, false); in mt8192_apll1_disable()
339 int mt8192_apll2_enable(struct mtk_base_afe *afe) in mt8192_apll2_enable() argument
341 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_apll2_enable()
345 apll2_mux_setting(afe, true); in mt8192_apll2_enable()
349 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_apll2_enable()
356 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", in mt8192_apll2_enable()
361 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, in mt8192_apll2_enable()
363 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1); in mt8192_apll2_enable()
365 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8192_apll2_enable()
373 void mt8192_apll2_disable(struct mtk_base_afe *afe) in mt8192_apll2_disable() argument
375 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_apll2_disable()
377 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE, in mt8192_apll2_disable()
381 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0); in mt8192_apll2_disable()
386 apll2_mux_setting(afe, false); in mt8192_apll2_disable()
389 int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll) in mt8192_get_apll_rate() argument
394 int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate) in mt8192_get_apll_by_rate() argument
399 int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name) in mt8192_get_apll_by_name() argument
566 int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate) in mt8192_mck_enable() argument
568 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_mck_enable()
569 int apll = mt8192_get_apll_by_rate(afe, rate); in mt8192_mck_enable()
580 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", in mt8192_mck_enable()
587 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n", in mt8192_mck_enable()
597 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n", in mt8192_mck_enable()
603 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n", in mt8192_mck_enable()
612 void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id) in mt8192_mck_disable() argument
614 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_mck_disable()
623 int mt8192_init_clock(struct mtk_base_afe *afe) in mt8192_init_clock() argument
625 struct mt8192_afe_private *afe_priv = afe->platform_priv; in mt8192_init_clock()
626 struct device_node *of_node = afe->dev->of_node; in mt8192_init_clock()
629 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk), in mt8192_init_clock()
635 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt8192_init_clock()
637 dev_warn(afe->dev, "%s devm_clk_get %s fail, ret %ld\n", in mt8192_init_clock()
647 dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n", in mt8192_init_clock()
655 dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n", in mt8192_init_clock()
663 dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n", in mt8192_init_clock()