Lines Matching full:27
33 #define PDN_TML_SFT 27
34 #define PDN_TML_MASK_SFT BIT(27)
326 #define GAIN1_TARGET_MASK_SFT GENMASK(27, 0)
339 #define GAIN2_TARGET_MASK_SFT GENMASK(27, 0)
343 #define AFE_GAIN1_CUR_MASK_SFT GENMASK(27, 0)
347 #define AFE_GAIN2_CUR_MASK_SFT GENMASK(27, 0)
358 #define PCM_DAI_PCM_LOOPBACK_SFT 27
359 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT BIT(27)
410 #define PCM1_SYNC_GLITCH_SFT 27
411 #define PCM1_SYNC_GLITCH_MASK_SFT BIT(27)
520 #define DL_2_CH1_SATURATION_EN_CTL_SFT 27
521 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT BIT(27)
565 #define UL_DMIC_PHASE_SEL_CH1_SFT 27
566 #define UL_DMIC_PHASE_SEL_CH1_MASK_SFT GENMASK(29, 27)
597 #define C_DAC_EN_CTL_SFT 27
598 #define C_DAC_EN_CTL_MASK_SFT BIT(27)
675 #define STF_BYPASS_MODE_DL3_SFT 27
676 #define STF_BYPASS_MODE_DL3_MASK_SFT BIT(27)
778 #define DL1_MODE_MASK_SFT GENMASK(27, 24)
807 #define DL2_MODE_MASK_SFT GENMASK(27, 24)
836 #define DL3_MODE_MASK_SFT GENMASK(27, 24)
865 #define DL4_MODE_MASK_SFT GENMASK(27, 24)
894 #define DL5_MODE_MASK_SFT GENMASK(27, 24)
923 #define DL6_MODE_MASK_SFT GENMASK(27, 24)
952 #define DL7_MODE_MASK_SFT GENMASK(27, 24)
981 #define DL8_MODE_MASK_SFT GENMASK(27, 24)
1010 #define DL12_MODE_MASK_SFT GENMASK(27, 24)
1042 #define AWB_MODE_MASK_SFT GENMASK(27, 24)
1068 #define AWB2_MODE_MASK_SFT GENMASK(27, 24)
1094 #define VUL_MODE_MASK_SFT GENMASK(27, 24)
1120 #define VUL12_MODE_MASK_SFT GENMASK(27, 24)
1149 #define VUL2_MODE_MASK_SFT GENMASK(27, 24)
1175 #define VUL3_MODE_MASK_SFT GENMASK(27, 24)
1201 #define VUL4_MODE_MASK_SFT GENMASK(27, 24)
1227 #define VUL5_MODE_MASK_SFT GENMASK(27, 24)
1253 #define VUL6_MODE_MASK_SFT GENMASK(27, 24)
1331 #define DAI2_MODE_MASK_SFT GENMASK(27, 24)
1454 #define IRQ6_MCU_MODE_MASK_SFT GENMASK(27, 24)
1480 #define IRQ14_MCU_MODE_MASK_SFT GENMASK(27, 24)
1506 #define IRQ22_MCU_MODE_MASK_SFT GENMASK(27, 24)
1600 #define IRQ27_MCU_EN_SFT 27
1634 #define IRQ27_MCU_SCP_EN_SFT 27
1668 #define IRQ27_MCU_DSP_EN_SFT 27
1878 #define AFE_ST_SFT 27
1879 #define AFE_ST_MASK_SFT GENMASK(31, 27)
1903 #define ETDM_IN1_CON0_REG_CH_NUM_MASK_SFT GENMASK(27, 23)
1956 #define ETDM_IN1_CON2_REG_SDATA_DELAY_0P5T_EN_SFT 27
1957 #define ETDM_IN1_CON2_REG_SDATA_DELAY_0P5T_EN_MASK_SFT BIT(27)
2107 #define ETDM_IN1_CON5_REG_LR_SWAP_11_SFT 27
2108 #define ETDM_IN1_CON5_REG_LR_SWAP_11_MASK_SFT BIT(27)