3  * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
32 #include "hi6210-i2s.h"
81 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)  in hi6210_write_reg()  argument
83 	writel(val, i2s->base + reg);  in hi6210_write_reg()
86 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)  in hi6210_read_reg()  argument
88 	return readl(i2s->base + reg);  in hi6210_read_reg()
94 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_startup()  local
99 	regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);  in hi6210_i2s_startup()
101 		regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));  in hi6210_i2s_startup()
103 	for (n = 0; n < i2s->clocks; n++) {  in hi6210_i2s_startup()
104 		ret = clk_prepare_enable(i2s->clk[n]);  in hi6210_i2s_startup()
109 	ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);  in hi6210_i2s_startup()
111 		dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",  in hi6210_i2s_startup()
117 	regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));  in hi6210_i2s_startup()
120 	regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));  in hi6210_i2s_startup()
123 	regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));  in hi6210_i2s_startup()
124 	regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));  in hi6210_i2s_startup()
126 	/* not interested in i2s irqs */  in hi6210_i2s_startup()
127 	val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);  in hi6210_i2s_startup()
129 	hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);  in hi6210_i2s_startup()
133 	val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);  in hi6210_i2s_startup()
135 	hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);  in hi6210_i2s_startup()
137 	val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);  in hi6210_i2s_startup()
139 	hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);  in hi6210_i2s_startup()
142 	val = hi6210_read_reg(i2s, HII2S_SW_RST_N);  in hi6210_i2s_startup()
146 	hi6210_write_reg(i2s, HII2S_SW_RST_N, val);  in hi6210_i2s_startup()
148 	val = hi6210_read_reg(i2s, HII2S_MISC_CFG);  in hi6210_i2s_startup()
149 	/* mux 11/12 = APB not i2s */  in hi6210_i2s_startup()
158 	hi6210_write_reg(i2s, HII2S_MISC_CFG, val);  in hi6210_i2s_startup()
160 	val = hi6210_read_reg(i2s, HII2S_SW_RST_N);  in hi6210_i2s_startup()
162 	hi6210_write_reg(i2s, HII2S_SW_RST_N, val);  in hi6210_i2s_startup()
168 		clk_disable_unprepare(i2s->clk[n]);  in hi6210_i2s_startup()
175 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_shutdown()  local
178 	for (n = 0; n < i2s->clocks; n++)  in hi6210_i2s_shutdown()
179 		clk_disable_unprepare(i2s->clk[n]);  in hi6210_i2s_shutdown()
181 	regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));  in hi6210_i2s_shutdown()
186 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_txctrl()  local
189 	spin_lock(&i2s->lock);  in hi6210_i2s_txctrl()
192 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_txctrl()
194 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_txctrl()
197 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_txctrl()
199 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_txctrl()
201 	spin_unlock(&i2s->lock);  in hi6210_i2s_txctrl()
206 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_rxctrl()  local
209 	spin_lock(&i2s->lock);  in hi6210_i2s_rxctrl()
211 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_rxctrl()
213 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_rxctrl()
215 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_rxctrl()
217 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_rxctrl()
219 	spin_unlock(&i2s->lock);  in hi6210_i2s_rxctrl()
224 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_set_fmt()  local
247 	i2s->format = fmt;  in hi6210_i2s_set_fmt()
248 	i2s->master = (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==  in hi6210_i2s_set_fmt()
258 	struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);  in hi6210_i2s_hw_params()  local
315 		i2s->bits = 32;  in hi6210_i2s_hw_params()
319 		i2s->bits = 16;  in hi6210_i2s_hw_params()
323 	i2s->rate = params_rate(params);  in hi6210_i2s_hw_params()
324 	i2s->channels = params_channels(params);  in hi6210_i2s_hw_params()
325 	i2s->channel_length = i2s->channels * i2s->bits;  in hi6210_i2s_hw_params()
327 	val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);  in hi6210_i2s_hw_params()
340 	hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);  in hi6210_i2s_hw_params()
343 	val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);  in hi6210_i2s_hw_params()
350 	hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);  in hi6210_i2s_hw_params()
353 	val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);  in hi6210_i2s_hw_params()
362 	hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);  in hi6210_i2s_hw_params()
365 	val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);  in hi6210_i2s_hw_params()
368 	hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);  in hi6210_i2s_hw_params()
370 	val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);  in hi6210_i2s_hw_params()
375 	hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);  in hi6210_i2s_hw_params()
378 	switch (i2s->format & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {  in hi6210_i2s_hw_params()
380 		i2s->master = false;  in hi6210_i2s_hw_params()
381 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
383 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
386 		i2s->master = true;  in hi6210_i2s_hw_params()
387 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
389 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
392 		WARN_ONCE(1, "Invalid i2s->fmt CLOCK_PROVIDER_MASK. This shouldn't happen\n");  in hi6210_i2s_hw_params()
396 	switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {  in hi6210_i2s_hw_params()
407 		WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");  in hi6210_i2s_hw_params()
411 	val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
415 	hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
418 	val = hi6210_read_reg(i2s, HII2S_CLK_SEL);  in hi6210_i2s_hw_params()
419 	val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */  in hi6210_i2s_hw_params()
421 	hi6210_write_reg(i2s, HII2S_CLK_SEL, val);  in hi6210_i2s_hw_params()
426 		dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;  in hi6210_i2s_hw_params()
428 		dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;  in hi6210_i2s_hw_params()
430 	switch (i2s->channels) {  in hi6210_i2s_hw_params()
432 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
434 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
437 		val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
439 		hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
444 	val = hi6210_read_reg(i2s, HII2S_I2S_CFG);  in hi6210_i2s_hw_params()
452 	hi6210_write_reg(i2s, HII2S_I2S_CFG, val);  in hi6210_i2s_hw_params()
455 	if (!i2s->master)  in hi6210_i2s_hw_params()
459 	val = hi6210_read_reg(i2s, HII2S_FS_CFG);  in hi6210_i2s_hw_params()
470 	hi6210_write_reg(i2s, HII2S_FS_CFG, val);  in hi6210_i2s_hw_params()
503 	struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);  in hi6210_i2s_dai_probe()  local
506 				  &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],  in hi6210_i2s_dai_probe()
507 				  &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);  in hi6210_i2s_dai_probe()
541 	.name = "hi6210_i2s-i2s",
549 	struct hi6210_i2s *i2s;  in hi6210_i2s_probe()  local
553 	i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);  in hi6210_i2s_probe()
554 	if (!i2s)  in hi6210_i2s_probe()
557 	i2s->dev = dev;  in hi6210_i2s_probe()
558 	spin_lock_init(&i2s->lock);  in hi6210_i2s_probe()
560 	i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in hi6210_i2s_probe()
561 	if (IS_ERR(i2s->base))  in hi6210_i2s_probe()
562 		return PTR_ERR(i2s->base);  in hi6210_i2s_probe()
564 	i2s->base_phys = (phys_addr_t)res->start;  in hi6210_i2s_probe()
565 	i2s->dai = hi6210_i2s_dai_init;  in hi6210_i2s_probe()
567 	dev_set_drvdata(dev, i2s);  in hi6210_i2s_probe()
569 	i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,  in hi6210_i2s_probe()
571 	if (IS_ERR(i2s->sysctrl))  in hi6210_i2s_probe()
572 		return PTR_ERR(i2s->sysctrl);  in hi6210_i2s_probe()
574 	i2s->clk[CLK_DACODEC] = devm_clk_get(dev, "dacodec");  in hi6210_i2s_probe()
575 	if (IS_ERR(i2s->clk[CLK_DACODEC]))  in hi6210_i2s_probe()
576 		return PTR_ERR(i2s->clk[CLK_DACODEC]);  in hi6210_i2s_probe()
577 	i2s->clocks++;  in hi6210_i2s_probe()
579 	i2s->clk[CLK_I2S_BASE] = devm_clk_get(dev, "i2s-base");  in hi6210_i2s_probe()
580 	if (IS_ERR(i2s->clk[CLK_I2S_BASE]))  in hi6210_i2s_probe()
581 		return PTR_ERR(i2s->clk[CLK_I2S_BASE]);  in hi6210_i2s_probe()
582 	i2s->clocks++;  in hi6210_i2s_probe()
589 					 &i2s->dai, 1);  in hi6210_i2s_probe()
594 	{ .compatible = "hisilicon,hi6210-i2s" },
610 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");