Lines Matching +full:imx8mp +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/reset.h>
18 #include "imx-pcm.h"
34 struct reset_control *reset; member
59 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
97 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
98 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
100 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
111 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
131 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
132 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
143 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
154 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_put()
171 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_activate_ctl()
177 return -ENOENT; in fsl_xcvr_activate_ctl()
179 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); in fsl_xcvr_activate_ctl()
184 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
186 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; in fsl_xcvr_activate_ctl()
188 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); in fsl_xcvr_activate_ctl()
198 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_mode_put()
199 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_mode_put()
200 struct snd_soc_card *card = dai->component->card; in fsl_xcvr_mode_put()
203 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_mode_put()
206 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_mode_put()
208 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_mode_put()
210 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); in fsl_xcvr_mode_put()
211 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = in fsl_xcvr_mode_put()
212 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); in fsl_xcvr_mode_put()
222 ucontrol->value.enumerated.item[0] = xcvr->mode; in fsl_xcvr_mode_get()
237 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_ai_write()
244 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); in fsl_xcvr_ai_write()
245 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); in fsl_xcvr_ai_write()
246 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); in fsl_xcvr_ai_write()
247 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); in fsl_xcvr_ai_write()
249 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, in fsl_xcvr_ai_write()
260 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_phy_pll()
272 return -EINVAL; in fsl_xcvr_en_phy_pll()
276 /* Release AI interface from reset */ in fsl_xcvr_en_phy_pll()
277 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_phy_pll()
309 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ in fsl_xcvr_en_phy_pll()
325 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_phy_pll()
334 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_en_phy_pll()
342 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); in fsl_xcvr_en_phy_pll()
353 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_en_aud_pll()
356 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
357 ret = clk_set_rate(xcvr->phy_clk, freq); in fsl_xcvr_en_aud_pll()
362 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_en_aud_pll()
368 /* Release AI interface from reset */ in fsl_xcvr_en_aud_pll()
369 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, in fsl_xcvr_en_aud_pll()
376 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ in fsl_xcvr_en_aud_pll()
401 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_prepare()
403 u32 r = substream->runtime->rate, ch = substream->runtime->channels; in fsl_xcvr_prepare()
407 switch (xcvr->mode) { in fsl_xcvr_prepare()
413 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", in fsl_xcvr_prepare()
418 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
421 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
426 * set SPDIF MODE - this flag is used to gate in fsl_xcvr_prepare()
436 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
442 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
448 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", in fsl_xcvr_prepare()
457 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, in fsl_xcvr_prepare()
461 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
466 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, in fsl_xcvr_prepare()
470 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); in fsl_xcvr_prepare()
475 /* clear CMDC RESET */ in fsl_xcvr_prepare()
483 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_prepare()
486 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); in fsl_xcvr_prepare()
490 /* set DPATH RESET */ in fsl_xcvr_prepare()
493 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); in fsl_xcvr_prepare()
495 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); in fsl_xcvr_prepare()
506 struct snd_pcm_runtime *rt = substream->runtime; in fsl_xcvr_constr()
526 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_startup()
529 if (xcvr->streams & BIT(substream->stream)) { in fsl_xcvr_startup()
530 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); in fsl_xcvr_startup()
531 return -EBUSY; in fsl_xcvr_startup()
534 switch (xcvr->mode) { in fsl_xcvr_startup()
548 xcvr->streams |= BIT(substream->stream); in fsl_xcvr_startup()
562 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_shutdown()
566 xcvr->streams &= ~BIT(substream->stream); in fsl_xcvr_shutdown()
569 if (!xcvr->streams) { in fsl_xcvr_shutdown()
572 (xcvr->mode == FSL_XCVR_MODE_ARC)); in fsl_xcvr_shutdown()
574 (xcvr->mode == FSL_XCVR_MODE_EARC)); in fsl_xcvr_shutdown()
576 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_shutdown()
579 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); in fsl_xcvr_shutdown()
584 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) in fsl_xcvr_shutdown()
588 if (xcvr->mode == FSL_XCVR_MODE_EARC) { in fsl_xcvr_shutdown()
589 /* set CMDC RESET */ in fsl_xcvr_shutdown()
594 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_shutdown()
596 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); in fsl_xcvr_shutdown()
605 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_xcvr_trigger()
613 switch (xcvr->mode) { in fsl_xcvr_trigger()
616 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
620 dev_err(dai->dev, "err updating isr %d\n", ret); in fsl_xcvr_trigger()
625 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
629 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
637 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
640 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); in fsl_xcvr_trigger()
644 /* clear DPATH RESET */ in fsl_xcvr_trigger()
645 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
649 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); in fsl_xcvr_trigger()
658 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_trigger()
662 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); in fsl_xcvr_trigger()
667 switch (xcvr->mode) { in fsl_xcvr_trigger()
669 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
673 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); in fsl_xcvr_trigger()
679 ret = regmap_write(xcvr->regmap, in fsl_xcvr_trigger()
683 dev_err(dai->dev, in fsl_xcvr_trigger()
692 return -EINVAL; in fsl_xcvr_trigger()
700 struct device *dev = &xcvr->pdev->dev; in fsl_xcvr_load_firmware()
705 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); in fsl_xcvr_load_firmware()
711 rem = fw->size; in fsl_xcvr_load_firmware()
717 return -ENOMEM; in fsl_xcvr_load_firmware()
721 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_load_firmware()
735 memcpy_toio(xcvr->ram_addr, fw->data + off, out); in fsl_xcvr_load_firmware()
736 rem -= out; in fsl_xcvr_load_firmware()
740 memset_io(xcvr->ram_addr + out, 0, size - out); in fsl_xcvr_load_firmware()
744 memset_io(xcvr->ram_addr, 0, size); in fsl_xcvr_load_firmware()
764 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); in fsl_xcvr_load_firmware()
771 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, in fsl_xcvr_load_firmware()
779 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_xcvr_type_iec958_info()
780 uinfo->count = 1; in fsl_xcvr_type_iec958_info()
788 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_iec958_bytes_info()
789 uinfo->count = sizeof_field(struct snd_aes_iec958, status); in fsl_xcvr_type_iec958_bytes_info()
800 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); in fsl_xcvr_rx_cs_get()
811 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); in fsl_xcvr_tx_cs_get()
822 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); in fsl_xcvr_tx_cs_put()
878 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); in fsl_xcvr_dai_probe()
894 .stream_name = "CPU-Playback",
903 .stream_name = "CPU-Capture",
914 .name = "fsl-xcvr-dai",
1056 struct device *dev = &xcvr->pdev->dev; in irq0_isr()
1057 struct regmap *regmap = xcvr->regmap; in irq0_isr()
1067 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in irq0_isr()
1072 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; in irq0_isr()
1073 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; in irq0_isr()
1076 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; in irq0_isr()
1077 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; in irq0_isr()
1083 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, in irq0_isr()
1084 sizeof(xcvr->rx_iec958.status)); in irq0_isr()
1086 val = *(u32 *)(xcvr->rx_iec958.status + i*4); in irq0_isr()
1087 *(u32 *)(xcvr->rx_iec958.status + i*4) = in irq0_isr()
1128 .fw_name = "imx/xcvr/xcvr-imx8mp.bin",
1132 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
1139 struct device *dev = &pdev->dev; in fsl_xcvr_probe()
1147 return -ENOMEM; in fsl_xcvr_probe()
1149 xcvr->pdev = pdev; in fsl_xcvr_probe()
1150 xcvr->soc_data = of_device_get_match_data(&pdev->dev); in fsl_xcvr_probe()
1152 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); in fsl_xcvr_probe()
1153 if (IS_ERR(xcvr->ipg_clk)) { in fsl_xcvr_probe()
1155 return PTR_ERR(xcvr->ipg_clk); in fsl_xcvr_probe()
1158 xcvr->phy_clk = devm_clk_get(dev, "phy"); in fsl_xcvr_probe()
1159 if (IS_ERR(xcvr->phy_clk)) { in fsl_xcvr_probe()
1161 return PTR_ERR(xcvr->phy_clk); in fsl_xcvr_probe()
1164 xcvr->spba_clk = devm_clk_get(dev, "spba"); in fsl_xcvr_probe()
1165 if (IS_ERR(xcvr->spba_clk)) { in fsl_xcvr_probe()
1167 return PTR_ERR(xcvr->spba_clk); in fsl_xcvr_probe()
1170 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); in fsl_xcvr_probe()
1171 if (IS_ERR(xcvr->pll_ipg_clk)) { in fsl_xcvr_probe()
1173 return PTR_ERR(xcvr->pll_ipg_clk); in fsl_xcvr_probe()
1176 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); in fsl_xcvr_probe()
1177 if (IS_ERR(xcvr->ram_addr)) in fsl_xcvr_probe()
1178 return PTR_ERR(xcvr->ram_addr); in fsl_xcvr_probe()
1184 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, in fsl_xcvr_probe()
1186 if (IS_ERR(xcvr->regmap)) { in fsl_xcvr_probe()
1188 PTR_ERR(xcvr->regmap)); in fsl_xcvr_probe()
1189 return PTR_ERR(xcvr->regmap); in fsl_xcvr_probe()
1192 xcvr->reset = devm_reset_control_get_exclusive(dev, NULL); in fsl_xcvr_probe()
1193 if (IS_ERR(xcvr->reset)) { in fsl_xcvr_probe()
1194 dev_err(dev, "failed to get XCVR reset control\n"); in fsl_xcvr_probe()
1195 return PTR_ERR(xcvr->reset); in fsl_xcvr_probe()
1203 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); in fsl_xcvr_probe()
1213 return -EINVAL; in fsl_xcvr_probe()
1215 xcvr->dma_prms_rx.chan_name = "rx"; in fsl_xcvr_probe()
1216 xcvr->dma_prms_tx.chan_name = "tx"; in fsl_xcvr_probe()
1217 xcvr->dma_prms_rx.addr = rx_res->start; in fsl_xcvr_probe()
1218 xcvr->dma_prms_tx.addr = tx_res->start; in fsl_xcvr_probe()
1219 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; in fsl_xcvr_probe()
1220 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; in fsl_xcvr_probe()
1224 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_probe()
1250 pm_runtime_disable(&pdev->dev); in fsl_xcvr_remove()
1264 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, in fsl_xcvr_runtime_suspend()
1269 /* Assert M0+ reset */ in fsl_xcvr_runtime_suspend()
1270 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_suspend()
1276 regcache_cache_only(xcvr->regmap, true); in fsl_xcvr_runtime_suspend()
1278 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_suspend()
1279 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_suspend()
1280 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_suspend()
1281 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_suspend()
1291 ret = reset_control_assert(xcvr->reset); in fsl_xcvr_runtime_resume()
1293 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); in fsl_xcvr_runtime_resume()
1297 ret = clk_prepare_enable(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1303 ret = clk_prepare_enable(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1309 ret = clk_prepare_enable(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1315 ret = clk_prepare_enable(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1321 regcache_cache_only(xcvr->regmap, false); in fsl_xcvr_runtime_resume()
1322 regcache_mark_dirty(xcvr->regmap); in fsl_xcvr_runtime_resume()
1323 ret = regcache_sync(xcvr->regmap); in fsl_xcvr_runtime_resume()
1330 ret = reset_control_deassert(xcvr->reset); in fsl_xcvr_runtime_resume()
1332 dev_err(dev, "failed to deassert M0+ reset.\n"); in fsl_xcvr_runtime_resume()
1342 /* Release M0+ reset */ in fsl_xcvr_runtime_resume()
1343 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, in fsl_xcvr_runtime_resume()
1356 clk_disable_unprepare(xcvr->spba_clk); in fsl_xcvr_runtime_resume()
1358 clk_disable_unprepare(xcvr->phy_clk); in fsl_xcvr_runtime_resume()
1360 clk_disable_unprepare(xcvr->pll_ipg_clk); in fsl_xcvr_runtime_resume()
1362 clk_disable_unprepare(xcvr->ipg_clk); in fsl_xcvr_runtime_resume()
1378 .name = "fsl,imx8mp-audio-xcvr",