Lines Matching +full:ssi +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
7 * Copyright 2007-2008 Freescale Semiconductor, Inc.
13 /* -- SSI Register Map -- */
15 /* SSI Transmit Data Register 0 */
17 /* SSI Transmit Data Register 1 */
19 /* SSI Receive Data Register 0 */
21 /* SSI Receive Data Register 1 */
23 /* SSI Control Register */
25 /* SSI Interrupt Status Register */
27 /* SSI Interrupt Enable Register */
29 /* SSI Transmit Configuration Register */
31 /* SSI Receive Configuration Register */
34 /* SSI Transmit Clock Control Register */
36 /* SSI Receive Clock Control Register */
39 /* SSI FIFO Control/Status Register */
42 * SSI Test Register (Intended for debugging purposes only)
49 * SSI Option Register (Intended for internal use only)
55 /* SSI AC97 Control Register */
57 /* SSI AC97 Command Address Register */
59 /* SSI AC97 Command Data Register */
61 /* SSI AC97 Tag Register */
63 /* SSI Transmit Time Slot Mask Register */
65 /* SSI Receive Time Slot Mask Register */
69 * SSI AC97 Channel Status Register
73 * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
77 /* SSI AC97 Channel Enable Register -- Set bits in SACCST */
79 /* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
82 /* -- SSI Register Field Maps -- */
84 /* SSI Control Register -- REG_SSI_SCR 0x10 */
101 /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
124 /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
151 /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
163 /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
177 * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
178 * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
187 (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
191 ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
195 ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
198 * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
200 * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
201 * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
236 /* SSI Test Register -- REG_SSI_STR 0x30 */
246 /* SSI Option Register -- REG_SSI_SOR 0x34 */
257 /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */