1 /* SPDX-License-Identifier: GPL-2.0 */
35 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
48 #define MICFIL_CTRL1_CHEN(ch)		BIT(ch)  argument
50 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
58 #define MICFIL_QSEL_VLOW2_QUALITY	4
63 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
67 #define MICFIL_STAT_CHXF(ch)		BIT(ch)  argument
69 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
72 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
73 #define MICFIL_FIFO_STAT_FIFOX_OVER(ch)	BIT(ch)  argument
74 #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)	BIT((ch) + 8)  argument
76 /* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
78 #define MICFIL_DC_CHX_SHIFT(ch)        ((ch) << 1)  argument
79 #define MICFIL_DC_CHX(ch)              GENMASK((((ch) << 1) + 1), ((ch) << 1))  argument
85 /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
89 #define MICFIL_VAD0_CTRL1_ST10		BIT(4)
95 /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
103 /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
108 /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
116 /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
119 #define MICFIL_VAD0_ZCD_ZCDAND		BIT(4)
123 /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
130 #define MICFIL_OUTGAIN_CHX_SHIFT(v)	(4 * (v))