Lines Matching refs:OUT
466 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk]; in fsl_asrc_config_pair()
469 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; in fsl_asrc_config_pair()
483 inrate, clk_index[ideal ? OUT : IN]); in fsl_asrc_config_pair()
489 clk = asrc_priv->asrck_clk[clk_index[OUT]]; in fsl_asrc_config_pair()
492 div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]); in fsl_asrc_config_pair()
494 div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]); in fsl_asrc_config_pair()
497 if (div[OUT] == 0 || (!ideal && !div_avail)) { in fsl_asrc_config_pair()
499 outrate, clk_index[OUT]); in fsl_asrc_config_pair()
503 div[OUT] = min_t(u32, 1024, div[OUT]); in fsl_asrc_config_pair()
526 ASRCSR_AOCS(index, clk_index[OUT])); in fsl_asrc_config_pair()
530 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); in fsl_asrc_config_pair()
672 rate[OUT] = out_rate; in fsl_asrc_select_clk()
688 if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) { in fsl_asrc_select_clk()
690 select_clk[OUT] = OUTCLK_ASRCK1_CLK; in fsl_asrc_select_clk()
694 config->outclk = select_clk[OUT]; in fsl_asrc_select_clk()
1152 asrc_priv->clk_map[OUT] = output_clk_map_imx35; in fsl_asrc_probe()
1155 asrc_priv->clk_map[OUT] = output_clk_map_imx53; in fsl_asrc_probe()
1170 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx]; in fsl_asrc_probe()
1173 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; in fsl_asrc_probe()