29 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)  in i2s_write_reg()  function
45 			i2s_write_reg(dev->i2s_base, TER(i), 0);  in i2s_disable_channels()
48 			i2s_write_reg(dev->i2s_base, RER(i), 0);  in i2s_disable_channels()
73 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);  in i2s_disable_irqs()
78 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);  in i2s_disable_irqs()
91 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);  in i2s_enable_irqs()
96 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);  in i2s_enable_irqs()
157 	i2s_write_reg(dev->i2s_base, IER, 1);  in i2s_start()
161 		i2s_write_reg(dev->i2s_base, ITER, 1);  in i2s_start()
163 		i2s_write_reg(dev->i2s_base, IRER, 1);  in i2s_start()
165 	i2s_write_reg(dev->i2s_base, CER, 1);  in i2s_start()
174 		i2s_write_reg(dev->i2s_base, ITER, 0);  in i2s_stop()
176 		i2s_write_reg(dev->i2s_base, IRER, 0);  in i2s_stop()
181 		i2s_write_reg(dev->i2s_base, CER, 0);  in i2s_stop()
182 		i2s_write_reg(dev->i2s_base, IER, 0);  in i2s_stop()
220 			i2s_write_reg(dev->i2s_base, TCR(ch_reg),  in dw_i2s_config()
222 			i2s_write_reg(dev->i2s_base, TFCR(ch_reg),  in dw_i2s_config()
224 			i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);  in dw_i2s_config()
226 			i2s_write_reg(dev->i2s_base, RCR(ch_reg),  in dw_i2s_config()
228 			i2s_write_reg(dev->i2s_base, RFCR(ch_reg),  in dw_i2s_config()
230 			i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);  in dw_i2s_config()
282 	i2s_write_reg(dev->i2s_base, CCR, dev->ccr);  in dw_i2s_hw_params()
320 		i2s_write_reg(dev->i2s_base, TXFFR, 1);  in dw_i2s_prepare()
322 		i2s_write_reg(dev->i2s_base, RXFFR, 1);  in dw_i2s_prepare()