Lines Matching +full:0 +full:x3b00
20 #define RT5682S_RESET 0x0000
21 #define RT5682S_VERSION_ID 0x00fd
22 #define RT5682S_VENDOR_ID 0x00fe
23 #define RT5682S_DEVICE_ID 0x00ff
25 #define RT5682S_HP_CTRL_1 0x0002
26 #define RT5682S_HP_CTRL_2 0x0003
27 #define RT5682S_HPL_GAIN 0x0005
28 #define RT5682S_HPR_GAIN 0x0006
30 #define RT5682S_I2C_CTRL 0x0008
33 #define RT5682S_CBJ_BST_CTRL 0x000b
34 #define RT5682S_CBJ_DET_CTRL 0x000f
35 #define RT5682S_CBJ_CTRL_1 0x0010
36 #define RT5682S_CBJ_CTRL_2 0x0011
37 #define RT5682S_CBJ_CTRL_3 0x0012
38 #define RT5682S_CBJ_CTRL_4 0x0013
39 #define RT5682S_CBJ_CTRL_5 0x0014
40 #define RT5682S_CBJ_CTRL_6 0x0015
41 #define RT5682S_CBJ_CTRL_7 0x0016
42 #define RT5682S_CBJ_CTRL_8 0x0017
44 #define RT5682S_DAC1_DIG_VOL 0x0019
45 #define RT5682S_STO1_ADC_DIG_VOL 0x001c
46 #define RT5682S_STO1_ADC_BOOST 0x001f
47 #define RT5682S_HP_IMP_GAIN_1 0x0022
48 #define RT5682S_HP_IMP_GAIN_2 0x0023
50 #define RT5682S_SIDETONE_CTRL 0x0024
51 #define RT5682S_STO1_ADC_MIXER 0x0026
52 #define RT5682S_AD_DA_MIXER 0x0029
53 #define RT5682S_STO1_DAC_MIXER 0x002a
54 #define RT5682S_A_DAC1_MUX 0x002b
55 #define RT5682S_DIG_INF2_DATA 0x0030
57 #define RT5682S_REC_MIXER 0x003c
58 #define RT5682S_CAL_REC 0x0044
60 #define RT5682S_HP_ANA_OST_CTRL_1 0x004b
61 #define RT5682S_HP_ANA_OST_CTRL_2 0x004c
62 #define RT5682S_HP_ANA_OST_CTRL_3 0x004d
64 #define RT5682S_PWR_DIG_1 0x0061
65 #define RT5682S_PWR_DIG_2 0x0062
66 #define RT5682S_PWR_ANLG_1 0x0063
67 #define RT5682S_PWR_ANLG_2 0x0064
68 #define RT5682S_PWR_ANLG_3 0x0065
69 #define RT5682S_PWR_MIXER 0x0066
71 #define RT5682S_MB_CTRL 0x0067
72 #define RT5682S_CLK_GATE_TCON_1 0x0068
73 #define RT5682S_CLK_GATE_TCON_2 0x0069
74 #define RT5682S_CLK_GATE_TCON_3 0x006a
76 #define RT5682S_CLK_DET 0x006b
78 #define RT5682S_RESET_LPF_CTRL 0x006c
79 #define RT5682S_RESET_HPF_CTRL 0x006d
81 #define RT5682S_DMIC_CTRL_1 0x006e
82 #define RT5682S_LPF_AD_DMIC 0x006f
84 #define RT5682S_I2S1_SDP 0x0070
85 #define RT5682S_I2S2_SDP 0x0071
86 #define RT5682S_ADDA_CLK_1 0x0073
87 #define RT5682S_ADDA_CLK_2 0x0074
88 #define RT5682S_I2S1_F_DIV_CTRL_1 0x0075
89 #define RT5682S_I2S1_F_DIV_CTRL_2 0x0076
91 #define RT5682S_TDM_CTRL 0x0079
92 #define RT5682S_TDM_ADDA_CTRL_1 0x007a
93 #define RT5682S_TDM_ADDA_CTRL_2 0x007b
94 #define RT5682S_DATA_SEL_CTRL_1 0x007c
95 #define RT5682S_TDM_TCON_CTRL_1 0x007e
96 #define RT5682S_TDM_TCON_CTRL_2 0x007f
98 #define RT5682S_GLB_CLK 0x0080
99 #define RT5682S_PLL_TRACK_1 0x0083
100 #define RT5682S_PLL_TRACK_2 0x0084
101 #define RT5682S_PLL_TRACK_3 0x0085
102 #define RT5682S_PLL_TRACK_4 0x0086
103 #define RT5682S_PLL_TRACK_5 0x0087
104 #define RT5682S_PLL_TRACK_6 0x0088
105 #define RT5682S_PLL_TRACK_11 0x008c
106 #define RT5682S_DEPOP_1 0x008e
107 #define RT5682S_HP_CHARGE_PUMP_1 0x008f
108 #define RT5682S_HP_CHARGE_PUMP_2 0x0091
109 #define RT5682S_HP_CHARGE_PUMP_3 0x0092
110 #define RT5682S_MICBIAS_1 0x0093
111 #define RT5682S_MICBIAS_2 0x0094
112 #define RT5682S_MICBIAS_3 0x0095
114 #define RT5682S_PLL_TRACK_12 0x0096
115 #define RT5682S_PLL_TRACK_14 0x0097
116 #define RT5682S_PLL_CTRL_1 0x0098
117 #define RT5682S_PLL_CTRL_2 0x0099
118 #define RT5682S_PLL_CTRL_3 0x009a
119 #define RT5682S_PLL_CTRL_4 0x009b
120 #define RT5682S_PLL_CTRL_5 0x009c
121 #define RT5682S_PLL_CTRL_6 0x009d
122 #define RT5682S_PLL_CTRL_7 0x009e
124 #define RT5682S_RC_CLK_CTRL 0x009f
125 #define RT5682S_I2S2_M_CLK_CTRL_1 0x00a0
126 #define RT5682S_I2S2_F_DIV_CTRL_1 0x00a3
127 #define RT5682S_I2S2_F_DIV_CTRL_2 0x00a4
129 #define RT5682S_IRQ_CTRL_1 0x00b6
130 #define RT5682S_IRQ_CTRL_2 0x00b7
131 #define RT5682S_IRQ_CTRL_3 0x00b8
132 #define RT5682S_IRQ_CTRL_4 0x00b9
133 #define RT5682S_INT_ST_1 0x00be
134 #define RT5682S_GPIO_CTRL_1 0x00c0
135 #define RT5682S_GPIO_CTRL_2 0x00c1
136 #define RT5682S_GPIO_ST 0x00c2
137 #define RT5682S_HP_AMP_DET_CTRL_1 0x00d0
138 #define RT5682S_MID_HP_AMP_DET 0x00d2
139 #define RT5682S_LOW_HP_AMP_DET 0x00d3
140 #define RT5682S_DELAY_BUF_CTRL 0x00d4
141 #define RT5682S_SV_ZCD_1 0x00d9
142 #define RT5682S_SV_ZCD_2 0x00da
143 #define RT5682S_IL_CMD_1 0x00db
144 #define RT5682S_IL_CMD_2 0x00dc
145 #define RT5682S_IL_CMD_3 0x00dd
146 #define RT5682S_IL_CMD_4 0x00de
147 #define RT5682S_IL_CMD_5 0x00df
148 #define RT5682S_IL_CMD_6 0x00e0
149 #define RT5682S_4BTN_IL_CMD_1 0x00e2
150 #define RT5682S_4BTN_IL_CMD_2 0x00e3
151 #define RT5682S_4BTN_IL_CMD_3 0x00e4
152 #define RT5682S_4BTN_IL_CMD_4 0x00e5
153 #define RT5682S_4BTN_IL_CMD_5 0x00e6
154 #define RT5682S_4BTN_IL_CMD_6 0x00e7
155 #define RT5682S_4BTN_IL_CMD_7 0x00e8
157 #define RT5682S_ADC_STO1_HP_CTRL_1 0x00ea
158 #define RT5682S_ADC_STO1_HP_CTRL_2 0x00eb
159 #define RT5682S_AJD1_CTRL 0x00f0
160 #define RT5682S_JD_CTRL_1 0x00f6
162 #define RT5682S_DUMMY_1 0x00fa
163 #define RT5682S_DUMMY_2 0x00fb
164 #define RT5682S_DUMMY_3 0x00fc
166 #define RT5682S_DAC_ADC_DIG_VOL1 0x0100
167 #define RT5682S_BIAS_CUR_CTRL_2 0x010b
168 #define RT5682S_BIAS_CUR_CTRL_3 0x010c
169 #define RT5682S_BIAS_CUR_CTRL_4 0x010d
170 #define RT5682S_BIAS_CUR_CTRL_5 0x010e
171 #define RT5682S_BIAS_CUR_CTRL_6 0x010f
172 #define RT5682S_BIAS_CUR_CTRL_7 0x0110
173 #define RT5682S_BIAS_CUR_CTRL_8 0x0111
174 #define RT5682S_BIAS_CUR_CTRL_9 0x0112
175 #define RT5682S_BIAS_CUR_CTRL_10 0x0113
176 #define RT5682S_VREF_REC_OP_FB_CAP_CTRL_1 0x0117
177 #define RT5682S_VREF_REC_OP_FB_CAP_CTRL_2 0x0118
178 #define RT5682S_CHARGE_PUMP_1 0x0125
179 #define RT5682S_DIG_IN_CTRL_1 0x0132
180 #define RT5682S_PAD_DRIVING_CTRL 0x0136
181 #define RT5682S_CHOP_DAC_1 0x0139
182 #define RT5682S_CHOP_DAC_2 0x013a
183 #define RT5682S_CHOP_ADC 0x013b
184 #define RT5682S_CALIB_ADC_CTRL 0x013c
185 #define RT5682S_VOL_TEST 0x013f
186 #define RT5682S_SPKVDD_DET_ST 0x0142
187 #define RT5682S_TEST_MODE_CTRL_1 0x0145
188 #define RT5682S_TEST_MODE_CTRL_2 0x0146
189 #define RT5682S_TEST_MODE_CTRL_3 0x0147
190 #define RT5682S_TEST_MODE_CTRL_4 0x0148
191 #define RT5682S_PLL_INTERNAL_1 0x0156
192 #define RT5682S_PLL_INTERNAL_2 0x0157
193 #define RT5682S_PLL_INTERNAL_3 0x0158
194 #define RT5682S_PLL_INTERNAL_4 0x0159
195 #define RT5682S_STO_NG2_CTRL_1 0x0160
196 #define RT5682S_STO_NG2_CTRL_2 0x0161
197 #define RT5682S_STO_NG2_CTRL_3 0x0162
198 #define RT5682S_STO_NG2_CTRL_4 0x0163
199 #define RT5682S_STO_NG2_CTRL_5 0x0164
200 #define RT5682S_STO_NG2_CTRL_6 0x0165
201 #define RT5682S_STO_NG2_CTRL_7 0x0166
202 #define RT5682S_STO_NG2_CTRL_8 0x0167
203 #define RT5682S_STO_NG2_CTRL_9 0x0168
204 #define RT5682S_STO_NG2_CTRL_10 0x0169
205 #define RT5682S_STO1_DAC_SIL_DET 0x0190
206 #define RT5682S_SIL_PSV_CTRL1 0x0194
207 #define RT5682S_SIL_PSV_CTRL2 0x0195
208 #define RT5682S_SIL_PSV_CTRL3 0x0197
209 #define RT5682S_SIL_PSV_CTRL4 0x0198
210 #define RT5682S_SIL_PSV_CTRL5 0x0199
211 #define RT5682S_HP_IMP_SENS_CTRL_1 0x01ac
212 #define RT5682S_HP_IMP_SENS_CTRL_2 0x01ad
213 #define RT5682S_HP_IMP_SENS_CTRL_3 0x01ae
214 #define RT5682S_HP_IMP_SENS_CTRL_4 0x01af
215 #define RT5682S_HP_IMP_SENS_CTRL_5 0x01b0
216 #define RT5682S_HP_IMP_SENS_CTRL_6 0x01b1
217 #define RT5682S_HP_IMP_SENS_CTRL_7 0x01b2
218 #define RT5682S_HP_IMP_SENS_CTRL_8 0x01b3
219 #define RT5682S_HP_IMP_SENS_CTRL_9 0x01b4
220 #define RT5682S_HP_IMP_SENS_CTRL_10 0x01b5
221 #define RT5682S_HP_IMP_SENS_CTRL_11 0x01b6
222 #define RT5682S_HP_IMP_SENS_CTRL_12 0x01b7
223 #define RT5682S_HP_IMP_SENS_CTRL_13 0x01b8
224 #define RT5682S_HP_IMP_SENS_CTRL_14 0x01b9
225 #define RT5682S_HP_IMP_SENS_CTRL_15 0x01ba
226 #define RT5682S_HP_IMP_SENS_CTRL_16 0x01bb
227 #define RT5682S_HP_IMP_SENS_CTRL_17 0x01bc
228 #define RT5682S_HP_IMP_SENS_CTRL_18 0x01bd
229 #define RT5682S_HP_IMP_SENS_CTRL_19 0x01be
230 #define RT5682S_HP_IMP_SENS_CTRL_20 0x01bf
231 #define RT5682S_HP_IMP_SENS_CTRL_21 0x01c0
232 #define RT5682S_HP_IMP_SENS_CTRL_22 0x01c1
233 #define RT5682S_HP_IMP_SENS_CTRL_23 0x01c2
234 #define RT5682S_HP_IMP_SENS_CTRL_24 0x01c3
235 #define RT5682S_HP_IMP_SENS_CTRL_25 0x01c4
236 #define RT5682S_HP_IMP_SENS_CTRL_26 0x01c5
237 #define RT5682S_HP_IMP_SENS_CTRL_27 0x01c6
238 #define RT5682S_HP_IMP_SENS_CTRL_28 0x01c7
239 #define RT5682S_HP_IMP_SENS_CTRL_29 0x01c8
240 #define RT5682S_HP_IMP_SENS_CTRL_30 0x01c9
241 #define RT5682S_HP_IMP_SENS_CTRL_31 0x01ca
242 #define RT5682S_HP_IMP_SENS_CTRL_32 0x01cb
243 #define RT5682S_HP_IMP_SENS_CTRL_33 0x01cc
244 #define RT5682S_HP_IMP_SENS_CTRL_34 0x01cd
245 #define RT5682S_HP_IMP_SENS_CTRL_35 0x01ce
246 #define RT5682S_HP_IMP_SENS_CTRL_36 0x01cf
247 #define RT5682S_HP_IMP_SENS_CTRL_37 0x01d0
248 #define RT5682S_HP_IMP_SENS_CTRL_38 0x01d1
249 #define RT5682S_HP_IMP_SENS_CTRL_39 0x01d2
250 #define RT5682S_HP_IMP_SENS_CTRL_40 0x01d3
251 #define RT5682S_HP_IMP_SENS_CTRL_41 0x01d4
252 #define RT5682S_HP_IMP_SENS_CTRL_42 0x01d5
253 #define RT5682S_HP_IMP_SENS_CTRL_43 0x01d6
254 #define RT5682S_HP_IMP_SENS_CTRL_44 0x01d7
255 #define RT5682S_HP_IMP_SENS_CTRL_45 0x01d8
256 #define RT5682S_HP_IMP_SENS_CTRL_46 0x01d9
257 #define RT5682S_HP_LOGIC_CTRL_1 0x01da
258 #define RT5682S_HP_LOGIC_CTRL_2 0x01db
259 #define RT5682S_HP_LOGIC_CTRL_3 0x01dc
260 #define RT5682S_HP_CALIB_CTRL_1 0x01de
261 #define RT5682S_HP_CALIB_CTRL_2 0x01df
262 #define RT5682S_HP_CALIB_CTRL_3 0x01e0
263 #define RT5682S_HP_CALIB_CTRL_4 0x01e1
264 #define RT5682S_HP_CALIB_CTRL_5 0x01e2
265 #define RT5682S_HP_CALIB_CTRL_6 0x01e3
266 #define RT5682S_HP_CALIB_CTRL_7 0x01e4
267 #define RT5682S_HP_CALIB_CTRL_8 0x01e5
268 #define RT5682S_HP_CALIB_CTRL_9 0x01e6
269 #define RT5682S_HP_CALIB_CTRL_10 0x01e7
270 #define RT5682S_HP_CALIB_CTRL_11 0x01e8
271 #define RT5682S_HP_CALIB_ST_1 0x01ea
272 #define RT5682S_HP_CALIB_ST_2 0x01eb
273 #define RT5682S_HP_CALIB_ST_3 0x01ec
274 #define RT5682S_HP_CALIB_ST_4 0x01ed
275 #define RT5682S_HP_CALIB_ST_5 0x01ee
276 #define RT5682S_HP_CALIB_ST_6 0x01ef
277 #define RT5682S_HP_CALIB_ST_7 0x01f0
278 #define RT5682S_HP_CALIB_ST_8 0x01f1
279 #define RT5682S_HP_CALIB_ST_9 0x01f2
280 #define RT5682S_HP_CALIB_ST_10 0x01f3
281 #define RT5682S_HP_CALIB_ST_11 0x01f4
282 #define RT5682S_SAR_IL_CMD_1 0x0210
283 #define RT5682S_SAR_IL_CMD_2 0x0211
284 #define RT5682S_SAR_IL_CMD_3 0x0212
285 #define RT5682S_SAR_IL_CMD_4 0x0213
286 #define RT5682S_SAR_IL_CMD_5 0x0214
287 #define RT5682S_SAR_IL_CMD_6 0x0215
288 #define RT5682S_SAR_IL_CMD_7 0x0216
289 #define RT5682S_SAR_IL_CMD_8 0x0217
290 #define RT5682S_SAR_IL_CMD_9 0x0218
291 #define RT5682S_SAR_IL_CMD_10 0x0219
292 #define RT5682S_SAR_IL_CMD_11 0x021a
293 #define RT5682S_SAR_IL_CMD_12 0x021b
294 #define RT5682S_SAR_IL_CMD_13 0x021c
295 #define RT5682S_SAR_IL_CMD_14 0x021d
296 #define RT5682S_DUMMY_4 0x02fa
297 #define RT5682S_DUMMY_5 0x02fb
298 #define RT5682S_DUMMY_6 0x02fc
299 #define RT5682S_VERSION_ID_HIDE 0x03fe
300 #define RT5682S_VERSION_ID_CUS 0x03ff
301 #define RT5682S_SCAN_CTL 0x0500
302 #define RT5682S_HP_AMP_DET 0x0600
303 #define RT5682S_BIAS_CUR_CTRL_11 0x0610
304 #define RT5682S_BIAS_CUR_CTRL_12 0x0611
305 #define RT5682S_BIAS_CUR_CTRL_13 0x0620
306 #define RT5682S_BIAS_CUR_CTRL_14 0x0621
307 #define RT5682S_BIAS_CUR_CTRL_15 0x0630
308 #define RT5682S_BIAS_CUR_CTRL_16 0x0631
309 #define RT5682S_BIAS_CUR_CTRL_17 0x0640
310 #define RT5682S_BIAS_CUR_CTRL_18 0x0641
311 #define RT5682S_I2C_TRANS_CTRL 0x07fa
312 #define RT5682S_DUMMY_7 0x08fa
313 #define RT5682S_DUMMY_8 0x08fb
314 #define RT5682S_DMIC_FLOAT_DET 0x0d00
315 #define RT5682S_HA_CMP_OP_1 0x1100
316 #define RT5682S_HA_CMP_OP_2 0x1101
317 #define RT5682S_HA_CMP_OP_3 0x1102
318 #define RT5682S_HA_CMP_OP_4 0x1103
319 #define RT5682S_HA_CMP_OP_5 0x1104
320 #define RT5682S_HA_CMP_OP_6 0x1105
321 #define RT5682S_HA_CMP_OP_7 0x1106
322 #define RT5682S_HA_CMP_OP_8 0x1107
323 #define RT5682S_HA_CMP_OP_9 0x1108
324 #define RT5682S_HA_CMP_OP_10 0x1109
325 #define RT5682S_HA_CMP_OP_11 0x110a
326 #define RT5682S_HA_CMP_OP_12 0x110b
327 #define RT5682S_HA_CMP_OP_13 0x110c
328 #define RT5682S_HA_CMP_OP_14 0x1111
329 #define RT5682S_HA_CMP_OP_15 0x1112
330 #define RT5682S_HA_CMP_OP_16 0x1113
331 #define RT5682S_HA_CMP_OP_17 0x1114
332 #define RT5682S_HA_CMP_OP_18 0x1115
333 #define RT5682S_HA_CMP_OP_19 0x1116
334 #define RT5682S_HA_CMP_OP_20 0x1117
335 #define RT5682S_HA_CMP_OP_21 0x1118
336 #define RT5682S_HA_CMP_OP_22 0x1119
337 #define RT5682S_HA_CMP_OP_23 0x111a
338 #define RT5682S_HA_CMP_OP_24 0x111b
339 #define RT5682S_HA_CMP_OP_25 0x111c
340 #define RT5682S_NEW_CBJ_DET_CTL_1 0x1401
341 #define RT5682S_NEW_CBJ_DET_CTL_2 0x1402
342 #define RT5682S_NEW_CBJ_DET_CTL_3 0x1403
343 #define RT5682S_NEW_CBJ_DET_CTL_4 0x1404
344 #define RT5682S_NEW_CBJ_DET_CTL_5 0x1406
345 #define RT5682S_NEW_CBJ_DET_CTL_6 0x1407
346 #define RT5682S_NEW_CBJ_DET_CTL_7 0x1408
347 #define RT5682S_NEW_CBJ_DET_CTL_8 0x1409
348 #define RT5682S_NEW_CBJ_DET_CTL_9 0x140a
349 #define RT5682S_NEW_CBJ_DET_CTL_10 0x140b
350 #define RT5682S_NEW_CBJ_DET_CTL_11 0x140c
351 #define RT5682S_NEW_CBJ_DET_CTL_12 0x140d
352 #define RT5682S_NEW_CBJ_DET_CTL_13 0x140e
353 #define RT5682S_NEW_CBJ_DET_CTL_14 0x140f
354 #define RT5682S_NEW_CBJ_DET_CTL_15 0x1410
355 #define RT5682S_NEW_CBJ_DET_CTL_16 0x1411
356 #define RT5682S_DA_FILTER_1 0x1801
357 #define RT5682S_DA_FILTER_2 0x1802
358 #define RT5682S_DA_FILTER_3 0x1803
359 #define RT5682S_DA_FILTER_4 0x1804
360 #define RT5682S_DA_FILTER_5 0x1805
361 #define RT5682S_CLK_SW_TEST_1 0x2c00
362 #define RT5682S_CLK_SW_TEST_2 0x3400
363 #define RT5682S_CLK_SW_TEST_3 0x3404
364 #define RT5682S_CLK_SW_TEST_4 0x3405
365 #define RT5682S_CLK_SW_TEST_5 0x3406
366 #define RT5682S_CLK_SW_TEST_6 0x3407
367 #define RT5682S_CLK_SW_TEST_7 0x3408
368 #define RT5682S_CLK_SW_TEST_8 0x3409
369 #define RT5682S_CLK_SW_TEST_9 0x340a
370 #define RT5682S_CLK_SW_TEST_10 0x340b
371 #define RT5682S_CLK_SW_TEST_11 0x340c
372 #define RT5682S_CLK_SW_TEST_12 0x340d
373 #define RT5682S_CLK_SW_TEST_13 0x340e
374 #define RT5682S_CLK_SW_TEST_14 0x340f
375 #define RT5682S_EFUSE_MANU_WRITE_1 0x3410
376 #define RT5682S_EFUSE_MANU_WRITE_2 0x3411
377 #define RT5682S_EFUSE_MANU_WRITE_3 0x3412
378 #define RT5682S_EFUSE_MANU_WRITE_4 0x3413
379 #define RT5682S_EFUSE_MANU_WRITE_5 0x3414
380 #define RT5682S_EFUSE_MANU_WRITE_6 0x3415
381 #define RT5682S_EFUSE_READ_1 0x3424
382 #define RT5682S_EFUSE_READ_2 0x3425
383 #define RT5682S_EFUSE_READ_3 0x3426
384 #define RT5682S_EFUSE_READ_4 0x3427
385 #define RT5682S_EFUSE_READ_5 0x3428
386 #define RT5682S_EFUSE_READ_6 0x3429
387 #define RT5682S_EFUSE_READ_7 0x342a
388 #define RT5682S_EFUSE_READ_8 0x342b
389 #define RT5682S_EFUSE_READ_9 0x342c
390 #define RT5682S_EFUSE_READ_10 0x342d
391 #define RT5682S_EFUSE_READ_11 0x342e
392 #define RT5682S_EFUSE_READ_12 0x342f
393 #define RT5682S_EFUSE_READ_13 0x3430
394 #define RT5682S_EFUSE_READ_14 0x3431
395 #define RT5682S_EFUSE_READ_15 0x3432
396 #define RT5682S_EFUSE_READ_16 0x3433
397 #define RT5682S_EFUSE_READ_17 0x3434
398 #define RT5682S_EFUSE_READ_18 0x3435
399 #define RT5682S_EFUSE_TIMING_CTL_1 0x3440
400 #define RT5682S_EFUSE_TIMING_CTL_2 0x3441
401 #define RT5682S_PILOT_DIG_CTL_1 0x3500
402 #define RT5682S_PILOT_DIG_CTL_2 0x3501
403 #define RT5682S_HP_AMP_DET_CTL_1 0x3b00
404 #define RT5682S_HP_AMP_DET_CTL_2 0x3b01
405 #define RT5682S_HP_AMP_DET_CTL_3 0x3b02
406 #define RT5682S_HP_AMP_DET_CTL_4 0x3b03
411 #define RT5682S_L_MUTE (0x1 << 15)
413 #define RT5682S_R_MUTE (0x1 << 7)
416 #define RT5682S_R_VOL_SFT 0
417 #define RT5682S_CLK_SRC_MCLK (0x0)
418 #define RT5682S_CLK_SRC_PLL1 (0x1)
419 #define RT5682S_CLK_SRC_PLL2 (0x2)
420 #define RT5682S_CLK_SRC_RCCLK (0x4) /* 25M */
423 /* Headphone Amp Control 2 (0x0003) */
424 #define RT5682S_HPO_L_PATH_MASK (0x1 << 14)
425 #define RT5682S_HPO_L_PATH_EN (0x1 << 14)
426 #define RT5682S_HPO_L_PATH_DIS (0x0 << 14)
427 #define RT5682S_HPO_R_PATH_MASK (0x1 << 13)
428 #define RT5682S_HPO_R_PATH_EN (0x1 << 13)
429 #define RT5682S_HPO_R_PATH_DIS (0x0 << 13)
430 #define RT5682S_HPO_SEL_IP_EN_SW (0x1)
431 #define RT5682S_HPO_IP_EN_GATING (0x1)
432 #define RT5682S_HPO_IP_NO_GATING (0x0)
434 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
435 #define RT5682S_G_HP (0xf << 8)
437 #define RT5682S_G_STO_DA_DMIX (0xf)
438 #define RT5682S_G_STO_DA_SFT 0
440 /* Embeeded Jack and Type Detection Control 2 (0x0010) */
441 #define RT5682S_EMB_JD_MASK (0x1 << 15)
442 #define RT5682S_EMB_JD_EN (0x1 << 15)
444 #define RT5682S_EMB_JD_RST (0x1 << 14)
445 #define RT5682S_JD_MODE (0x1 << 13)
447 #define RT5682S_DET_TYPE (0x1 << 12)
449 #define RT5682S_POLA_EXT_JD_MASK (0x1 << 11)
450 #define RT5682S_POLA_EXT_JD_LOW (0x1 << 11)
451 #define RT5682S_POLA_EXT_JD_HIGH (0x0 << 11)
452 #define RT5682S_SEL_FAST_OFF_MASK (0x3 << 9)
454 #define RT5682S_POL_FAST_OFF_MASK (0x1 << 8)
455 #define RT5682S_POL_FAST_OFF_HIGH (0x1 << 8)
456 #define RT5682S_POL_FAST_OFF_LOW (0x0 << 8)
457 #define RT5682S_FAST_OFF_MASK (0x1 << 7)
458 #define RT5682S_FAST_OFF_EN (0x1 << 7)
459 #define RT5682S_FAST_OFF_DIS (0x0 << 7)
460 #define RT5682S_VREF_POW_MASK (0x1 << 6)
461 #define RT5682S_VREF_POW_FSM (0x0 << 6)
462 #define RT5682S_VREF_POW_REG (0x1 << 6)
464 #define RT5682S_MB1_PATH_MASK (0x1 << 5)
465 #define RT5682S_CTRL_MB1_REG (0x1 << 5)
466 #define RT5682S_CTRL_MB1_FSM (0x0 << 5)
468 #define RT5682S_MB2_PATH_MASK (0x1 << 4)
469 #define RT5682S_CTRL_MB2_REG (0x1 << 4)
470 #define RT5682S_CTRL_MB2_FSM (0x0 << 4)
471 #define RT5682S_TRIG_JD_MASK (0x1 << 3)
472 #define RT5682S_TRIG_JD_HIGH (0x1 << 3)
473 #define RT5682S_TRIG_JD_LOW (0x0 << 3)
474 #define RT5682S_MIC_CAP_MASK (0x1 << 1)
475 #define RT5682S_MIC_CAP_HS (0x1 << 1)
476 #define RT5682S_MIC_CAP_HP (0x0 << 1)
477 #define RT5682S_MIC_CAP_SRC_MASK (0x1)
478 #define RT5682S_MIC_CAP_SRC_REG (0x1)
479 #define RT5682S_MIC_CAP_SRC_ANA (0x0)
481 /* Embeeded Jack and Type Detection Control 3 (0x0011) */
482 #define RT5682S_SEL_CBJ_TYPE_SLOW (0x1 << 15)
483 #define RT5682S_SEL_CBJ_TYPE_NORM (0x0 << 15)
484 #define RT5682S_SEL_CBJ_TYPE_MASK (0x1 << 15)
485 #define RT5682S_POW_BG_MB1_MASK (0x1 << 13)
486 #define RT5682S_POW_BG_MB1_REG (0x1 << 13)
487 #define RT5682S_POW_BG_MB1_FSM (0x0 << 13)
488 #define RT5682S_POW_BG_MB2_MASK (0x1 << 12)
489 #define RT5682S_POW_BG_MB2_REG (0x1 << 12)
490 #define RT5682S_POW_BG_MB2_FSM (0x0 << 12)
491 #define RT5682S_EXT_JD_SRC (0x7 << 4)
493 #define RT5682S_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
494 #define RT5682S_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
495 #define RT5682S_EXT_JD_SRC_JDH (0x2 << 4)
496 #define RT5682S_EXT_JD_SRC_JDL (0x3 << 4)
497 #define RT5682S_EXT_JD_SRC_MANUAL (0x4 << 4)
498 #define RT5682S_JACK_TYPE_MASK (0x3)
500 /* Combo Jack and Type Detection Control 4 (0x0012) */
501 #define RT5682S_CBJ_IN_BUF_MASK (0x1 << 7)
502 #define RT5682S_CBJ_IN_BUF_EN (0x1 << 7)
503 #define RT5682S_CBJ_IN_BUF_DIS (0x0 << 7)
506 /* Combo Jack and Type Detection Control 5 (0x0013) */
507 #define RT5682S_SEL_SHT_MID_TON_MASK (0x3 << 12)
508 #define RT5682S_SEL_SHT_MID_TON_2 (0x0 << 12)
509 #define RT5682S_SEL_SHT_MID_TON_3 (0x1 << 12)
510 #define RT5682S_CBJ_JD_TEST_MASK (0x1 << 6)
511 #define RT5682S_CBJ_JD_TEST_NORM (0x0 << 6)
512 #define RT5682S_CBJ_JD_TEST_MODE (0x1 << 6)
514 /* Combo Jack and Type Detection Control 6 (0x0014) */
515 #define RT5682S_JD_FAST_OFF_SRC_MASK (0x7 << 8)
516 #define RT5682S_JD_FAST_OFF_SRC_JDH (0x6 << 8)
517 #define RT5682S_JD_FAST_OFF_SRC_GPIO6 (0x5 << 8)
518 #define RT5682S_JD_FAST_OFF_SRC_GPIO5 (0x4 << 8)
519 #define RT5682S_JD_FAST_OFF_SRC_GPIO4 (0x3 << 8)
520 #define RT5682S_JD_FAST_OFF_SRC_GPIO3 (0x2 << 8)
521 #define RT5682S_JD_FAST_OFF_SRC_GPIO2 (0x1 << 8)
522 #define RT5682S_JD_FAST_OFF_SRC_GPIO1 (0x0 << 8)
524 /* DAC1 Digital Volume (0x0019) */
525 #define RT5682S_DAC_L1_VOL_MASK (0xff << 8)
527 #define RT5682S_DAC_R1_VOL_MASK (0xff)
528 #define RT5682S_DAC_R1_VOL_SFT 0
530 /* ADC Digital Volume Control (0x001c) */
531 #define RT5682S_ADC_L_VOL_MASK (0x7f << 8)
533 #define RT5682S_ADC_R_VOL_MASK (0x7f)
534 #define RT5682S_ADC_R_VOL_SFT 0
536 /* Stereo1 ADC Boost Gain Control (0x001f) */
537 #define RT5682S_STO1_ADC_L_BST_MASK (0x3 << 14)
539 #define RT5682S_STO1_ADC_R_BST_MASK (0x3 << 12)
542 /* Sidetone Control (0x0024) */
543 #define RT5682S_ST_SRC_SEL (0x1 << 8)
545 #define RT5682S_ST_EN_MASK (0x1 << 6)
546 #define RT5682S_ST_DIS (0x0 << 6)
547 #define RT5682S_ST_EN (0x1 << 6)
550 /* Stereo1 ADC Mixer Control (0x0026) */
551 #define RT5682S_M_STO1_ADC_L1 (0x1 << 15)
553 #define RT5682S_M_STO1_ADC_L2 (0x1 << 14)
555 #define RT5682S_STO1_ADC1L_SRC_MASK (0x1 << 13)
557 #define RT5682S_STO1_ADC1_SRC_ADC (0x1 << 13)
558 #define RT5682S_STO1_ADC1_SRC_DACMIX (0x0 << 13)
559 #define RT5682S_STO1_ADC2L_SRC_MASK (0x1 << 12)
561 #define RT5682S_STO1_ADCL_SRC_MASK (0x3 << 10)
563 #define RT5682S_M_STO1_ADC_R1 (0x1 << 7)
565 #define RT5682S_M_STO1_ADC_R2 (0x1 << 6)
567 #define RT5682S_STO1_ADC1R_SRC_MASK (0x1 << 5)
569 #define RT5682S_STO1_ADC2R_SRC_MASK (0x1 << 4)
571 #define RT5682S_STO1_ADCR_SRC_MASK (0x3 << 2)
574 /* ADC Mixer to DAC Mixer Control (0x0029) */
575 #define RT5682S_M_ADCMIX_L (0x1 << 15)
577 #define RT5682S_M_DAC1_L (0x1 << 14)
579 #define RT5682S_M_ADCMIX_R (0x1 << 7)
581 #define RT5682S_M_DAC1_R (0x1 << 6)
584 /* Stereo1 DAC Mixer Control (0x002a) */
585 #define RT5682S_M_DAC_L1_STO_L (0x1 << 15)
587 #define RT5682S_G_DAC_L1_STO_L_MASK (0x1 << 14)
589 #define RT5682S_M_DAC_R1_STO_L (0x1 << 13)
591 #define RT5682S_G_DAC_R1_STO_L_MASK (0x1 << 12)
593 #define RT5682S_M_DAC_L1_STO_R (0x1 << 7)
595 #define RT5682S_G_DAC_L1_STO_R_MASK (0x1 << 6)
597 #define RT5682S_M_DAC_R1_STO_R (0x1 << 5)
599 #define RT5682S_G_DAC_R1_STO_R_MASK (0x1 << 4)
602 /* Analog DAC1 Input Source Control (0x002b) */
603 #define RT5682S_M_ST_STO_L (0x1 << 9)
605 #define RT5682S_M_ST_STO_R (0x1 << 8)
607 #define RT5682S_DAC_L1_SRC_MASK (0x1 << 4)
609 #define RT5682S_DAC_R1_SRC_MASK (0x1)
610 #define RT5682S_A_DACR1_SFT 0
612 /* Digital Interface Data Control (0x0030) */
613 #define RT5682S_IF2_DAC_SEL_MASK (0x3 << 2)
615 #define RT5682S_IF2_ADC_SEL_MASK (0x3 << 0)
616 #define RT5682S_IF2_ADC_SEL_SFT 0
618 /* REC Left/Right Mixer Control 2 (0x003c) */
619 #define RT5682S_BST_CBJ_MASK (0x3f << 8)
621 #define RT5682S_M_CBJ_RM1_L (0x1 << 7)
623 #define RT5682S_M_CBJ_RM1_R (0x1 << 6)
626 /* REC Left/Right Mixer Calibration Control(0x0044) */
628 #define RT5682S_PWR_RM1_L_BIT 0
630 /* Power Management for Digital 1 (0x0061) */
631 #define RT5682S_PWR_I2S1 (0x1 << 15)
633 #define RT5682S_PWR_I2S2 (0x1 << 14)
635 #define RT5682S_PRE_CHR_DAC_L1 (0x1 << 13)
637 #define RT5682S_PRE_CHR_DAC_R1 (0x1 << 12)
639 #define RT5682S_PWR_DAC_L1 (0x1 << 11)
641 #define RT5682S_PWR_DAC_R1 (0x1 << 10)
643 #define RT5682S_PWR_LDO (0x1 << 8)
645 #define RT5682S_PWR_D2S_L (0x1 << 7)
647 #define RT5682S_PWR_D2S_R (0x1 << 6)
649 #define RT5682S_PWR_ADC_L1 (0x1 << 4)
651 #define RT5682S_PWR_ADC_R1 (0x1 << 3)
653 #define RT5682S_EFUSE_SW_EN (0x1 << 2)
654 #define RT5682S_EFUSE_SW_DIS (0x0 << 2)
655 #define RT5682S_PWR_EFUSE (0x1 << 1)
657 #define RT5682S_DIG_GATE_CTRL (0x1 << 0)
658 #define RT5682S_DIG_GATE_CTRL_SFT 0
660 /* Power Management for Digital 2 (0x0062) */
661 #define RT5682S_PWR_ADC_S1F (0x1 << 15)
663 #define RT5682S_PWR_DAC_S1F (0x1 << 10)
665 #define RT5682S_DLDO_I_LIMIT_MASK (0x1 << 7)
666 #define RT5682S_DLDO_I_LIMIT_EN (0x1 << 7)
667 #define RT5682S_DLDO_I_LIMIT_DIS (0x0 << 7)
668 #define RT5682S_DLDO_I_BIAS_SEL_4 (0x1 << 6)
669 #define RT5682S_DLDO_I_BIAS_SEL_0 (0x0 << 6)
670 #define RT5682S_DLDO_REG_TEST_1 (0x1 << 5)
671 #define RT5682S_DLDO_REG_TEST_0 (0x0 << 5)
672 #define RT5682S_DLDO_SRC_REG (0x1 << 4)
673 #define RT5682S_DLDO_SRC_EFUSE (0x0 << 4)
675 /* Power Management for Analog 1 (0x0063) */
676 #define RT5682S_PWR_VREF1 (0x1 << 15)
678 #define RT5682S_PWR_FV1 (0x1 << 14)
680 #define RT5682S_PWR_VREF2 (0x1 << 13)
682 #define RT5682S_PWR_FV2 (0x1 << 12)
684 #define RT5682S_LDO1_DBG_MASK (0x3 << 10)
685 #define RT5682S_PWR_MB (0x1 << 9)
687 #define RT5682S_PWR_BG (0x1 << 7)
689 #define RT5682S_LDO1_BYPASS_MASK (0x1 << 6)
690 #define RT5682S_LDO1_BYPASS (0x1 << 6)
691 #define RT5682S_LDO1_NOT_BYPASS (0x0 << 6)
693 /* Power Management for Analog 2 (0x0064) */
694 #define RT5682S_PWR_MCLK0_WD (0x1 << 15)
696 #define RT5682S_PWR_MCLK1_WD (0x1 << 14)
698 #define RT5682S_RST_MCLK0 (0x1 << 13)
700 #define RT5682S_RST_MCLK1 (0x1 << 12)
702 #define RT5682S_PWR_MB1 (0x1 << 11)
703 #define RT5682S_PWR_MB1_PWR_DOWN (0x0 << 11)
705 #define RT5682S_PWR_MB2 (0x1 << 10)
706 #define RT5682S_PWR_MB2_PWR_DOWN (0x0 << 10)
708 #define RT5682S_PWR_JD_MASK (0x1 << 0)
709 #define RT5682S_PWR_JD_ENABLE (0x1 << 0)
710 #define RT5682S_PWR_JD_DISABLE (0x0 << 0)
712 /* Power Management for Analog 3 (0x0065) */
713 #define RT5682S_PWR_LDO_PLLA (0x1 << 15)
715 #define RT5682S_PWR_LDO_PLLB (0x1 << 14)
717 #define RT5682S_PWR_BIAS_PLLA (0x1 << 13)
719 #define RT5682S_PWR_BIAS_PLLB (0x1 << 12)
721 #define RT5682S_PWR_CBJ (0x1 << 9)
723 #define RT5682S_RSTB_PLLB (0x1 << 7)
725 #define RT5682S_RSTB_PLLA (0x1 << 6)
727 #define RT5682S_PWR_PLLB (0x1 << 5)
729 #define RT5682S_PWR_PLLA (0x1 << 4)
731 #define RT5682S_PWR_LDO_MB2 (0x1 << 2)
733 #define RT5682S_PWR_LDO_MB1 (0x1 << 1)
735 #define RT5682S_PWR_BGLDO (0x1 << 0)
736 #define RT5682S_PWR_BGLDO_BIT 0
738 /* Power Management for Mixer (0x0066) */
739 #define RT5682S_PWR_CLK_COMP_8FS (0x1 << 15)
741 #define RT5682S_DBG_BGLDO_MASK (0x3 << 12)
743 #define RT5682S_DBG_BGLDO_MB1_MASK (0x3 << 10)
745 #define RT5682S_DBG_BGLDO_MB2_MASK (0x3 << 8)
747 #define RT5682S_DLDO_BGLDO_MASK (0x3 << 6)
749 #define RT5682S_PWR_STO1_DAC_L (0x1 << 5)
751 #define RT5682S_PWR_STO1_DAC_R (0x1 << 4)
753 #define RT5682S_DVO_BGLDO_MB1_MASK (0x3 << 2)
755 #define RT5682S_DVO_BGLDO_MB2_MASK (0x3 << 0)
757 /* MCLK and System Clock Detection Control (0x006b) */
758 #define RT5682S_SYS_CLK_DET (0x1 << 15)
760 #define RT5682S_PLL1_CLK_DET (0x1 << 14)
763 /* Digital Microphone Control 1 (0x006e) */
764 #define RT5682S_DMIC_1_EN_MASK (0x1 << 15)
766 #define RT5682S_DMIC_1_DIS (0x0 << 15)
767 #define RT5682S_DMIC_1_EN (0x1 << 15)
768 #define RT5682S_FIFO_CLK_DIV_MASK (0x7 << 12)
769 #define RT5682S_FIFO_CLK_DIV_2 (0x1 << 12)
770 #define RT5682S_DMIC_1_DP_MASK (0x3 << 4)
772 #define RT5682S_DMIC_1_DP_GPIO2 (0x0 << 4)
773 #define RT5682S_DMIC_1_DP_GPIO5 (0x1 << 4)
774 #define RT5682S_DMIC_CLK_MASK (0xf << 0)
775 #define RT5682S_DMIC_CLK_SFT 0
777 /* I2S1 Audio Serial Data Port Control (0x0070) */
778 #define RT5682S_SEL_ADCDAT_MASK (0x1 << 15)
779 #define RT5682S_SEL_ADCDAT_OUT (0x0 << 15)
780 #define RT5682S_SEL_ADCDAT_IN (0x1 << 15)
782 #define RT5682S_I2S1_TX_CHL_MASK (0x7 << 12)
784 #define RT5682S_I2S1_TX_CHL_16 (0x0 << 12)
785 #define RT5682S_I2S1_TX_CHL_20 (0x1 << 12)
786 #define RT5682S_I2S1_TX_CHL_24 (0x2 << 12)
787 #define RT5682S_I2S1_TX_CHL_32 (0x3 << 12)
788 #define RT5682S_I2S1_TX_CHL_8 (0x4 << 12)
789 #define RT5682S_I2S1_RX_CHL_MASK (0x7 << 8)
791 #define RT5682S_I2S1_RX_CHL_16 (0x0 << 8)
792 #define RT5682S_I2S1_RX_CHL_20 (0x1 << 8)
793 #define RT5682S_I2S1_RX_CHL_24 (0x2 << 8)
794 #define RT5682S_I2S1_RX_CHL_32 (0x3 << 8)
795 #define RT5682S_I2S1_RX_CHL_8 (0x4 << 8)
796 #define RT5682S_I2S1_MONO_MASK (0x1 << 7)
797 #define RT5682S_I2S1_MONO_EN (0x1 << 7)
798 #define RT5682S_I2S1_MONO_DIS (0x0 << 7)
799 #define RT5682S_I2S1_DL_MASK (0x7 << 4)
801 #define RT5682S_I2S1_DL_16 (0x0 << 4)
802 #define RT5682S_I2S1_DL_20 (0x1 << 4)
803 #define RT5682S_I2S1_DL_24 (0x2 << 4)
804 #define RT5682S_I2S1_DL_32 (0x3 << 4)
805 #define RT5682S_I2S1_DL_8 (0x4 << 4)
807 /* I2S1/2 Audio Serial Data Port Control (0x0071) */
808 #define RT5682S_I2S2_MS_MASK (0x1 << 15)
810 #define RT5682S_I2S2_MS_M (0x0 << 15)
811 #define RT5682S_I2S2_MS_S (0x1 << 15)
812 #define RT5682S_I2S2_PIN_CFG_MASK (0x1 << 14)
814 #define RT5682S_I2S2_OUT_MASK (0x1 << 9)
816 #define RT5682S_I2S2_OUT_UM (0x0 << 9)
817 #define RT5682S_I2S2_OUT_M (0x1 << 9)
818 #define RT5682S_I2S_BP_MASK (0x1 << 8)
820 #define RT5682S_I2S_BP_NOR (0x0 << 8)
821 #define RT5682S_I2S_BP_INV (0x1 << 8)
822 #define RT5682S_I2S2_MONO_MASK (0x1 << 7)
823 #define RT5682S_I2S2_MONO_EN (0x1 << 7)
824 #define RT5682S_I2S2_MONO_DIS (0x0 << 7)
825 #define RT5682S_I2S2_DL_MASK (0x7 << 4)
827 #define RT5682S_I2S2_DL_8 (0x0 << 4)
828 #define RT5682S_I2S2_DL_16 (0x1 << 4)
829 #define RT5682S_I2S2_DL_20 (0x2 << 4)
830 #define RT5682S_I2S2_DL_24 (0x3 << 4)
831 #define RT5682S_I2S2_DL_32 (0x4 << 4)
832 #define RT5682S_I2S_DF_MASK (0x7)
833 #define RT5682S_I2S_DF_SFT 0
834 #define RT5682S_I2S_DF_I2S (0x0)
835 #define RT5682S_I2S_DF_LEFT (0x1)
836 #define RT5682S_I2S_DF_PCM_A (0x2)
837 #define RT5682S_I2S_DF_PCM_B (0x3)
838 #define RT5682S_I2S_DF_PCM_A_N (0x6)
839 #define RT5682S_I2S_DF_PCM_B_N (0x7)
841 /* ADC/DAC Clock Control 1 (0x0073) */
842 #define RT5682S_ADC_OSR_MASK (0xf << 12)
844 #define RT5682S_ADC_OSR_D_1 (0x0 << 12)
845 #define RT5682S_ADC_OSR_D_2 (0x1 << 12)
846 #define RT5682S_ADC_OSR_D_4 (0x2 << 12)
847 #define RT5682S_ADC_OSR_D_6 (0x3 << 12)
848 #define RT5682S_ADC_OSR_D_8 (0x4 << 12)
849 #define RT5682S_ADC_OSR_D_12 (0x5 << 12)
850 #define RT5682S_ADC_OSR_D_16 (0x6 << 12)
851 #define RT5682S_ADC_OSR_D_24 (0x7 << 12)
852 #define RT5682S_ADC_OSR_D_32 (0x8 << 12)
853 #define RT5682S_ADC_OSR_D_48 (0x9 << 12)
854 #define RT5682S_I2S_M_D_MASK (0xf << 8)
856 #define RT5682S_I2S_M_D_1 (0x0 << 8)
857 #define RT5682S_I2S_M_D_2 (0x1 << 8)
858 #define RT5682S_I2S_M_D_3 (0x2 << 8)
859 #define RT5682S_I2S_M_D_4 (0x3 << 8)
860 #define RT5682S_I2S_M_D_6 (0x4 << 8)
861 #define RT5682S_I2S_M_D_8 (0x5 << 8)
862 #define RT5682S_I2S_M_D_12 (0x6 << 8)
863 #define RT5682S_I2S_M_D_16 (0x7 << 8)
864 #define RT5682S_I2S_M_D_24 (0x8 << 8)
865 #define RT5682S_I2S_M_D_32 (0x9 << 8)
866 #define RT5682S_I2S_M_D_48 (0x10 << 8)
867 #define RT5682S_I2S_M_CLK_SRC_MASK (0x7 << 4)
869 #define RT5682S_DAC_OSR_MASK (0xf << 0)
870 #define RT5682S_DAC_OSR_SFT 0
871 #define RT5682S_DAC_OSR_D_1 (0x0 << 0)
872 #define RT5682S_DAC_OSR_D_2 (0x1 << 0)
873 #define RT5682S_DAC_OSR_D_4 (0x2 << 0)
874 #define RT5682S_DAC_OSR_D_6 (0x3 << 0)
875 #define RT5682S_DAC_OSR_D_8 (0x4 << 0)
876 #define RT5682S_DAC_OSR_D_12 (0x5 << 0)
877 #define RT5682S_DAC_OSR_D_16 (0x6 << 0)
878 #define RT5682S_DAC_OSR_D_24 (0x7 << 0)
879 #define RT5682S_DAC_OSR_D_32 (0x8 << 0)
880 #define RT5682S_DAC_OSR_D_48 (0x9 << 0)
882 /* ADC/DAC Clock Control 2 (0x0074) */
883 #define RT5682S_I2S2_BCLK_MS2_MASK (0x1 << 11)
885 #define RT5682S_I2S2_BCLK_MS2_32 (0x0 << 11)
886 #define RT5682S_I2S2_BCLK_MS2_64 (0x1 << 11)
889 /* TDM control 1 (0x0079) */
890 #define RT5682S_TDM_TX_CH_MASK (0x3 << 12)
891 #define RT5682S_TDM_TX_CH_2 (0x0 << 12)
892 #define RT5682S_TDM_TX_CH_4 (0x1 << 12)
893 #define RT5682S_TDM_TX_CH_6 (0x2 << 12)
894 #define RT5682S_TDM_TX_CH_8 (0x3 << 12)
895 #define RT5682S_TDM_RX_CH_MASK (0x3 << 8)
896 #define RT5682S_TDM_RX_CH_2 (0x0 << 8)
897 #define RT5682S_TDM_RX_CH_4 (0x1 << 8)
898 #define RT5682S_TDM_RX_CH_6 (0x2 << 8)
899 #define RT5682S_TDM_RX_CH_8 (0x3 << 8)
900 #define RT5682S_TDM_ADC_LCA_MASK (0x7 << 4)
902 #define RT5682S_TDM_ADC_DL_MASK (0x3 << 0)
903 #define RT5682S_TDM_ADC_DL_SFT 0
905 /* TDM control 2 (0x007a) */
912 /* TDM control 3 (0x007b) */
913 #define RT5682S_TDM_EN (0x1 << 7)
915 /* TDM/I2S control (0x007e) */
916 #define RT5682S_TDM_S_BP_MASK (0x1 << 15)
918 #define RT5682S_TDM_S_BP_NOR (0x0 << 15)
919 #define RT5682S_TDM_S_BP_INV (0x1 << 15)
920 #define RT5682S_TDM_S_LP_MASK (0x1 << 14)
922 #define RT5682S_TDM_S_LP_NOR (0x0 << 14)
923 #define RT5682S_TDM_S_LP_INV (0x1 << 14)
924 #define RT5682S_TDM_DF_MASK (0x7 << 11)
926 #define RT5682S_TDM_DF_I2S (0x0 << 11)
927 #define RT5682S_TDM_DF_LEFT (0x1 << 11)
928 #define RT5682S_TDM_DF_PCM_A (0x2 << 11)
929 #define RT5682S_TDM_DF_PCM_B (0x3 << 11)
930 #define RT5682S_TDM_DF_PCM_A_N (0x6 << 11)
931 #define RT5682S_TDM_DF_PCM_B_N (0x7 << 11)
932 #define RT5682S_TDM_BCLK_MS1_MASK (0x3 << 8)
934 #define RT5682S_TDM_BCLK_MS1_32 (0x0 << 8)
935 #define RT5682S_TDM_BCLK_MS1_64 (0x1 << 8)
936 #define RT5682S_TDM_BCLK_MS1_128 (0x2 << 8)
937 #define RT5682S_TDM_BCLK_MS1_256 (0x3 << 8)
938 #define RT5682S_TDM_BCLK_MS1_16 (0x4 << 8)
939 #define RT5682S_TDM_CL_MASK (0x3 << 4)
940 #define RT5682S_TDM_CL_16 (0x0 << 4)
941 #define RT5682S_TDM_CL_20 (0x1 << 4)
942 #define RT5682S_TDM_CL_24 (0x2 << 4)
943 #define RT5682S_TDM_CL_32 (0x3 << 4)
944 #define RT5682S_TDM_M_BP_MASK (0x1 << 2)
946 #define RT5682S_TDM_M_BP_NOR (0x0 << 2)
947 #define RT5682S_TDM_M_BP_INV (0x1 << 2)
948 #define RT5682S_TDM_M_LP_MASK (0x1 << 1)
950 #define RT5682S_TDM_M_LP_NOR (0x0 << 1)
951 #define RT5682S_TDM_M_LP_INV (0x1 << 1)
952 #define RT5682S_TDM_MS_MASK (0x1 << 0)
953 #define RT5682S_TDM_MS_SFT 0
954 #define RT5682S_TDM_MS_S (0x0 << 0)
955 #define RT5682S_TDM_MS_M (0x1 << 0)
957 /* Global Clock Control (0x0080) */
958 #define RT5682S_SCLK_SRC_MASK (0x7 << 13)
960 #define RT5682S_PLL_SRC_MASK (0x3 << 8)
962 #define RT5682S_PLL_SRC_MCLK (0x0 << 8)
963 #define RT5682S_PLL_SRC_BCLK1 (0x1 << 8)
964 #define RT5682S_PLL_SRC_RC (0x3 << 8)
966 /* PLL tracking mode 1 (0x0083) */
967 #define RT5682S_DA_ASRC_MASK (0x1 << 13)
969 #define RT5682S_DAC_STO1_ASRC_MASK (0x1 << 12)
971 #define RT5682S_AD_ASRC_MASK (0x1 << 8)
973 #define RT5682S_AD_ASRC_SEL_MASK (0x1 << 4)
975 #define RT5682S_DMIC_ASRC_MASK (0x1 << 3)
977 #define RT5682S_ADC_STO1_ASRC_MASK (0x1 << 2)
979 #define RT5682S_DA_ASRC_SEL_MASK (0x1 << 0)
980 #define RT5682S_DA_ASRC_SEL_SFT 0
982 /* PLL tracking mode 2 3 (0x0084)(0x0085)*/
983 #define RT5682S_FILTER_CLK_SEL_MASK (0x7 << 12)
985 #define RT5682S_FILTER_CLK_DIV_MASK (0xf << 8)
988 /* ASRC Control 4 (0x0086) */
989 #define RT5682S_ASRCIN_FTK_N1_MASK (0x3 << 14)
991 #define RT5682S_ASRCIN_FTK_N2_MASK (0x3 << 12)
993 #define RT5682S_ASRCIN_FTK_M1_MASK (0x7 << 8)
995 #define RT5682S_ASRCIN_FTK_M2_MASK (0x7 << 4)
998 /* ASRC Control 11 (0x008c) */
999 #define RT5682S_ASRCIN_AUTO_CLKOUT_MASK (0x1 << 5)
1000 #define RT5682S_ASRCIN_AUTO_CLKOUT_EN (0x1 << 5)
1001 #define RT5682S_ASRCIN_AUTO_CLKOUT_DIS (0x0 << 5)
1002 #define RT5682S_ASRCIN_AUTO_RST_MASK (0x1 << 4)
1003 #define RT5682S_ASRCIN_AUTO_RST_EN (0x1 << 4)
1004 #define RT5682S_ASRCIN_AUTO_RST_DIS (0x0 << 4)
1005 #define RT5682S_SEL_LRCK_DET_MASK (0x3)
1006 #define RT5682S_SEL_LRCK_DET_DIV8 (0x3)
1007 #define RT5682S_SEL_LRCK_DET_DIV4 (0x2)
1008 #define RT5682S_SEL_LRCK_DET_DIV2 (0x1)
1009 #define RT5682S_SEL_LRCK_DET_DIV1 (0x0)
1011 /* Depop Mode Control 1 (0x008e) */
1012 #define RT5682S_OUT_HP_L_EN (0x1 << 6)
1013 #define RT5682S_OUT_HP_R_EN (0x1 << 5)
1014 #define RT5682S_LDO_PUMP_EN (0x1 << 4)
1016 #define RT5682S_PUMP_EN (0x1 << 3)
1018 #define RT5682S_CAPLESS_L_EN (0x1 << 1)
1020 #define RT5682S_CAPLESS_R_EN (0x1 << 0)
1021 #define RT5682S_CAPLESS_R_EN_SFT 0
1023 /* Depop Mode Control 2 (0x8f) */
1024 #define RT5682S_RAMP_MASK (0x1 << 12)
1026 #define RT5682S_RAMP_DIS (0x0 << 12)
1027 #define RT5682S_RAMP_EN (0x1 << 12)
1028 #define RT5682S_BPS_MASK (0x1 << 11)
1030 #define RT5682S_BPS_DIS (0x0 << 11)
1031 #define RT5682S_BPS_EN (0x1 << 11)
1032 #define RT5682S_FAST_UPDN_MASK (0x1 << 10)
1034 #define RT5682S_FAST_UPDN_DIS (0x0 << 10)
1035 #define RT5682S_FAST_UPDN_EN (0x1 << 10)
1036 #define RT5682S_VLO_MASK (0x1 << 7)
1038 #define RT5682S_VLO_3V (0x0 << 7)
1039 #define RT5682S_VLO_33V (0x1 << 7)
1041 /* HPOUT charge pump 1 (0x0091) */
1042 #define RT5682S_OSW_L_MASK (0x1 << 11)
1044 #define RT5682S_OSW_L_DIS (0x0 << 11)
1045 #define RT5682S_OSW_L_EN (0x1 << 11)
1046 #define RT5682S_OSW_R_MASK (0x1 << 10)
1048 #define RT5682S_OSW_R_DIS (0x0 << 10)
1049 #define RT5682S_OSW_R_EN (0x1 << 10)
1050 #define RT5682S_PM_HP_MASK (0x3 << 8)
1052 #define RT5682S_PM_HP_LV (0x0 << 8)
1053 #define RT5682S_PM_HP_MV (0x1 << 8)
1054 #define RT5682S_PM_HP_HV (0x2 << 8)
1056 /* Micbias Control1 (0x93) */
1057 #define RT5682S_MIC1_OV_MASK (0x3 << 14)
1059 #define RT5682S_MIC1_OV_2V7 (0x0 << 14)
1060 #define RT5682S_MIC1_OV_2V4 (0x1 << 14)
1061 #define RT5682S_MIC1_OV_2V25 (0x3 << 14)
1062 #define RT5682S_MIC1_OV_1V8 (0x4 << 14)
1063 #define RT5682S_MIC2_OV_MASK (0x3 << 8)
1065 #define RT5682S_MIC2_OV_2V7 (0x0 << 8)
1066 #define RT5682S_MIC2_OV_2V4 (0x1 << 8)
1067 #define RT5682S_MIC2_OV_2V25 (0x3 << 8)
1068 #define RT5682S_MIC2_OV_1V8 (0x4 << 8)
1070 /* Micbias Control2 (0x0094) */
1071 #define RT5682S_PWR_CLK25M_MASK (0x1 << 9)
1073 #define RT5682S_PWR_CLK25M_PD (0x0 << 9)
1074 #define RT5682S_PWR_CLK25M_PU (0x1 << 9)
1075 #define RT5682S_PWR_CLK1M_MASK (0x1 << 8)
1077 #define RT5682S_PWR_CLK1M_PD (0x0 << 8)
1078 #define RT5682S_PWR_CLK1M_PU (0x1 << 8)
1080 /* PLL M/N/K Code Control 1 (0x0098) */
1081 #define RT5682S_PLLA_N_MASK (0x1ff << 0)
1083 /* PLL M/N/K Code Control 2 (0x0099) */
1084 #define RT5682S_PLLA_M_MASK (0x1f << 8)
1086 #define RT5682S_PLLA_K_MASK (0x1f << 0)
1088 /* PLL M/N/K Code Control 3 (0x009a) */
1089 #define RT5682S_PLLB_N_MASK (0x3ff << 0)
1091 /* PLL M/N/K Code Control 4 (0x009b) */
1092 #define RT5682S_PLLB_M_MASK (0x1f << 8)
1094 #define RT5682S_PLLB_K_MASK (0x1f << 0)
1096 /* PLL M/N/K Code Control 6 (0x009d) */
1097 #define RT5682S_PLLB_SEL_PS_MASK (0x1 << 13)
1099 #define RT5682S_PLLB_BYP_PS_MASK (0x1 << 12)
1101 #define RT5682S_PLLB_M_BP_MASK (0x1 << 11)
1103 #define RT5682S_PLLB_K_BP_MASK (0x1 << 10)
1105 #define RT5682S_PLLA_M_BP_MASK (0x1 << 7)
1107 #define RT5682S_PLLA_K_BP_MASK (0x1 << 6)
1110 /* PLL M/N/K Code Control 7 (0x009e) */
1111 #define RT5682S_PLLB_SRC_MASK (0x1)
1112 #define RT5682S_PLLB_SRC_DFIN (0x1)
1113 #define RT5682S_PLLB_SRC_PLLA (0x0)
1115 /* RC Clock Control (0x009f) */
1116 #define RT5682S_POW_IRQ (0x1 << 15)
1117 #define RT5682S_POW_JDH (0x1 << 14)
1119 /* I2S2 Master Mode Clock Control 1 (0x00a0) */
1120 #define RT5682S_I2S2_M_CLK_SRC_MASK (0x7 << 4)
1122 #define RT5682S_I2S2_M_D_MASK (0xf << 0)
1123 #define RT5682S_I2S2_M_D_1 (0x0)
1124 #define RT5682S_I2S2_M_D_2 (0x1)
1125 #define RT5682S_I2S2_M_D_3 (0x2)
1126 #define RT5682S_I2S2_M_D_4 (0x3)
1127 #define RT5682S_I2S2_M_D_6 (0x4)
1128 #define RT5682S_I2S2_M_D_8 (0x5)
1129 #define RT5682S_I2S2_M_D_12 (0x6)
1130 #define RT5682S_I2S2_M_D_16 (0x7)
1131 #define RT5682S_I2S2_M_D_24 (0x8)
1132 #define RT5682S_I2S2_M_D_32 (0x9)
1133 #define RT5682S_I2S2_M_D_48 (0xa)
1134 #define RT5682S_I2S2_M_D_SFT 0
1136 /* IRQ Control 1 (0x00b6) */
1137 #define RT5682S_JD1_PULSE_EN_MASK (0x1 << 10)
1139 #define RT5682S_JD1_PULSE_DIS (0x0 << 10)
1140 #define RT5682S_JD1_PULSE_EN (0x1 << 10)
1142 /* IRQ Control 2 (0x00b7) */
1143 #define RT5682S_JD1_EN_MASK (0x1 << 15)
1145 #define RT5682S_JD1_DIS (0x0 << 15)
1146 #define RT5682S_JD1_EN (0x1 << 15)
1147 #define RT5682S_JD1_POL_MASK (0x1 << 13)
1148 #define RT5682S_JD1_POL_NOR (0x0 << 13)
1149 #define RT5682S_JD1_POL_INV (0x1 << 13)
1150 #define RT5682S_JD1_IRQ_MASK (0x1 << 10)
1151 #define RT5682S_JD1_IRQ_LEV (0x0 << 10)
1152 #define RT5682S_JD1_IRQ_PUL (0x1 << 10)
1154 /* IRQ Control 3 (0x00b8) */
1155 #define RT5682S_IL_IRQ_MASK (0x1 << 7)
1156 #define RT5682S_IL_IRQ_DIS (0x0 << 7)
1157 #define RT5682S_IL_IRQ_EN (0x1 << 7)
1158 #define RT5682S_IL_IRQ_TYPE_MASK (0x1 << 4)
1159 #define RT5682S_IL_IRQ_LEV (0x0 << 4)
1160 #define RT5682S_IL_IRQ_PUL (0x1 << 4)
1162 /* GPIO Control 1 (0x00c0) */
1163 #define RT5682S_GP1_PIN_MASK (0x3 << 14)
1165 #define RT5682S_GP1_PIN_GPIO1 (0x0 << 14)
1166 #define RT5682S_GP1_PIN_IRQ (0x1 << 14)
1167 #define RT5682S_GP1_PIN_DMIC_CLK (0x2 << 14)
1168 #define RT5682S_GP2_PIN_MASK (0x3 << 12)
1170 #define RT5682S_GP2_PIN_GPIO2 (0x0 << 12)
1171 #define RT5682S_GP2_PIN_LRCK2 (0x1 << 12)
1172 #define RT5682S_GP2_PIN_DMIC_SDA (0x2 << 12)
1173 #define RT5682S_GP3_PIN_MASK (0x3 << 10)
1175 #define RT5682S_GP3_PIN_GPIO3 (0x0 << 10)
1176 #define RT5682S_GP3_PIN_BCLK2 (0x1 << 10)
1177 #define RT5682S_GP3_PIN_DMIC_CLK (0x2 << 10)
1178 #define RT5682S_GP4_PIN_MASK (0x3 << 8)
1180 #define RT5682S_GP4_PIN_GPIO4 (0x0 << 8)
1181 #define RT5682S_GP4_PIN_ADCDAT1 (0x1 << 8)
1182 #define RT5682S_GP4_PIN_DMIC_CLK (0x2 << 8)
1183 #define RT5682S_GP4_PIN_ADCDAT2 (0x3 << 8)
1184 #define RT5682S_GP5_PIN_MASK (0x3 << 6)
1186 #define RT5682S_GP5_PIN_GPIO5 (0x0 << 6)
1187 #define RT5682S_GP5_PIN_DACDAT1 (0x1 << 6)
1188 #define RT5682S_GP5_PIN_DMIC_SDA (0x2 << 6)
1189 #define RT5682S_GP6_PIN_MASK (0x1 << 5)
1191 #define RT5682S_GP6_PIN_GPIO6 (0x0 << 5)
1192 #define RT5682S_GP6_PIN_LRCK1 (0x1 << 5)
1194 /* GPIO Control 2 (0x00c1)*/
1195 #define RT5682S_GP1_PF_MASK (0x1 << 15)
1196 #define RT5682S_GP1_PF_IN (0x0 << 15)
1197 #define RT5682S_GP1_PF_OUT (0x1 << 15)
1198 #define RT5682S_GP1_OUT_MASK (0x1 << 14)
1199 #define RT5682S_GP1_OUT_L (0x0 << 14)
1200 #define RT5682S_GP1_OUT_H (0x1 << 14)
1201 #define RT5682S_GP2_PF_MASK (0x1 << 13)
1202 #define RT5682S_GP2_PF_IN (0x0 << 13)
1203 #define RT5682S_GP2_PF_OUT (0x1 << 13)
1204 #define RT5682S_GP2_OUT_MASK (0x1 << 12)
1205 #define RT5682S_GP2_OUT_L (0x0 << 12)
1206 #define RT5682S_GP2_OUT_H (0x1 << 12)
1207 #define RT5682S_GP3_PF_MASK (0x1 << 11)
1208 #define RT5682S_GP3_PF_IN (0x0 << 11)
1209 #define RT5682S_GP3_PF_OUT (0x1 << 11)
1210 #define RT5682S_GP3_OUT_MASK (0x1 << 10)
1211 #define RT5682S_GP3_OUT_L (0x0 << 10)
1212 #define RT5682S_GP3_OUT_H (0x1 << 10)
1213 #define RT5682S_GP4_PF_MASK (0x1 << 9)
1214 #define RT5682S_GP4_PF_IN (0x0 << 9)
1215 #define RT5682S_GP4_PF_OUT (0x1 << 9)
1216 #define RT5682S_GP4_OUT_MASK (0x1 << 8)
1217 #define RT5682S_GP4_OUT_L (0x0 << 8)
1218 #define RT5682S_GP4_OUT_H (0x1 << 8)
1219 #define RT5682S_GP5_PF_MASK (0x1 << 7)
1220 #define RT5682S_GP5_PF_IN (0x0 << 7)
1221 #define RT5682S_GP5_PF_OUT (0x1 << 7)
1222 #define RT5682S_GP5_OUT_MASK (0x1 << 6)
1223 #define RT5682S_GP5_OUT_L (0x0 << 6)
1224 #define RT5682S_GP5_OUT_H (0x1 << 6)
1225 #define RT5682S_GP6_PF_MASK (0x1 << 5)
1226 #define RT5682S_GP6_PF_IN (0x0 << 5)
1227 #define RT5682S_GP6_PF_OUT (0x1 << 5)
1228 #define RT5682S_GP6_OUT_MASK (0x1 << 4)
1229 #define RT5682S_GP6_OUT_L (0x0 << 4)
1230 #define RT5682S_GP6_OUT_H (0x1 << 4)
1232 /* GPIO Status (0x00c2) */
1233 #define RT5682S_GP6_ST (0x1 << 6)
1234 #define RT5682S_GP5_ST (0x1 << 5)
1235 #define RT5682S_GP4_ST (0x1 << 4)
1236 #define RT5682S_GP3_ST (0x1 << 3)
1237 #define RT5682S_GP2_ST (0x1 << 2)
1238 #define RT5682S_GP1_ST (0x1 << 1)
1240 /* Soft volume and zero cross control 1 (0x00d9) */
1241 #define RT5682S_ZCD_MASK (0x1 << 10)
1243 #define RT5682S_ZCD_PD (0x0 << 10)
1244 #define RT5682S_ZCD_PU (0x1 << 10)
1246 /* 4 Button Inline Command Control 2 (0x00e3) */
1247 #define RT5682S_4BTN_IL_MASK (0x1 << 15)
1248 #define RT5682S_4BTN_IL_EN (0x1 << 15)
1249 #define RT5682S_4BTN_IL_DIS (0x0 << 15)
1250 #define RT5682S_4BTN_IL_RST_MASK (0x1 << 14)
1251 #define RT5682S_4BTN_IL_NOR (0x1 << 14)
1252 #define RT5682S_4BTN_IL_RST (0x0 << 14)
1254 /* 4 Button Inline Command Control 3~6 (0x00e5~0x00e8) */
1255 #define RT5682S_4BTN_IL_HOLD_WIN_MASK (0x7f << 8)
1257 #define RT5682S_4BTN_IL_CLICK_WIN_MASK (0x7f)
1258 #define RT5682S_4BTN_IL_CLICK_WIN_SFT 0
1260 /* Analog JD Control (0x00f0) */
1261 #define RT5682S_JDH_RS_MASK (0x1 << 4)
1262 #define RT5682S_JDH_NO_PLUG (0x1 << 4)
1263 #define RT5682S_JDH_PLUG (0x0 << 4)
1265 /* Charge Pump Internal Register1 (0x0125) */
1266 #define RT5682S_CP_CLK_HP_MASK (0x3 << 4)
1267 #define RT5682S_CP_CLK_HP_100KHZ (0x0 << 4)
1268 #define RT5682S_CP_CLK_HP_200KHZ (0x1 << 4)
1269 #define RT5682S_CP_CLK_HP_300KHZ (0x2 << 4)
1270 #define RT5682S_CP_CLK_HP_600KHZ (0x3 << 4)
1272 /* Pad Driving Control (0x0136) */
1273 #define RT5682S_PAD_DRV_GP1_MASK (0x1 << 14)
1274 #define RT5682S_PAD_DRV_GP1_HIGH (0x1 << 14)
1275 #define RT5682S_PAD_DRV_GP1_LOW (0x0 << 14)
1276 #define RT5682S_PAD_DRV_GP2_MASK (0x1 << 12)
1277 #define RT5682S_PAD_DRV_GP2_HIGH (0x1 << 12)
1278 #define RT5682S_PAD_DRV_GP2_LOW (0x0 << 12)
1279 #define RT5682S_PAD_DRV_GP3_MASK (0x1 << 10)
1280 #define RT5682S_PAD_DRV_GP3_HIGH (0x1 << 10)
1281 #define RT5682S_PAD_DRV_GP3_LOW (0x0 << 10)
1282 #define RT5682S_PAD_DRV_GP4_MASK (0x1 << 8)
1283 #define RT5682S_PAD_DRV_GP4_HIGH (0x1 << 8)
1284 #define RT5682S_PAD_DRV_GP4_LOW (0x0 << 8)
1285 #define RT5682S_PAD_DRV_GP5_MASK (0x1 << 6)
1286 #define RT5682S_PAD_DRV_GP5_HIGH (0x1 << 6)
1287 #define RT5682S_PAD_DRV_GP5_LOW (0x0 << 6)
1288 #define RT5682S_PAD_DRV_GP6_MASK (0x1 << 4)
1289 #define RT5682S_PAD_DRV_GP6_HIGH (0x1 << 4)
1290 #define RT5682S_PAD_DRV_GP6_LOW (0x0 << 4)
1292 /* Chopper and Clock control for DAC (0x013a)*/
1293 #define RT5682S_CKXEN_DAC1_MASK (0x1 << 13)
1295 #define RT5682S_CKGEN_DAC1_MASK (0x1 << 12)
1298 /* Chopper and Clock control for ADC (0x013b)*/
1299 #define RT5682S_CKXEN_ADC1_MASK (0x1 << 13)
1301 #define RT5682S_CKGEN_ADC1_MASK (0x1 << 12)
1304 /* Volume test (0x013f)*/
1305 #define RT5682S_SEL_CLK_VOL_MASK (0x1 << 15)
1306 #define RT5682S_SEL_CLK_VOL_EN (0x1 << 15)
1307 #define RT5682S_SEL_CLK_VOL_DIS (0x0 << 15)
1309 /* Test Mode Control 1 (0x0145) */
1310 #define RT5682S_AD2DA_LB_MASK (0x1 << 10)
1313 /* Stereo Noise Gate Control 1 (0x0160) */
1314 #define RT5682S_NG2_EN_MASK (0x1 << 15)
1315 #define RT5682S_NG2_EN (0x1 << 15)
1316 #define RT5682S_NG2_DIS (0x0 << 15)
1318 /* Stereo1 DAC Silence Detection Control (0x0190) */
1319 #define RT5682S_DEB_STO_DAC_MASK (0x7 << 4)
1320 #define RT5682S_DEB_80_MS (0x0 << 4)
1322 /* HP Behavior Logic Control 2 (0x01db) */
1323 #define RT5682S_HP_SIG_SRC_MASK (0x3)
1324 #define RT5682S_HP_SIG_SRC_1BIT_CTL (0x3)
1325 #define RT5682S_HP_SIG_SRC_REG (0x2)
1326 #define RT5682S_HP_SIG_SRC_IMPE_REG (0x1)
1327 #define RT5682S_HP_SIG_SRC_DC_CALI (0x0)
1329 /* SAR ADC Inline Command Control 1 (0x0210) */
1330 #define RT5682S_SAR_BUTDET_MASK (0x1 << 15)
1331 #define RT5682S_SAR_BUTDET_EN (0x1 << 15)
1332 #define RT5682S_SAR_BUTDET_DIS (0x0 << 15)
1333 #define RT5682S_SAR_BUTDET_POW_MASK (0x1 << 14)
1334 #define RT5682S_SAR_BUTDET_POW_SAV (0x1 << 14)
1335 #define RT5682S_SAR_BUTDET_POW_NORM (0x0 << 14)
1336 #define RT5682S_SAR_BUTDET_RST_MASK (0x1 << 13)
1337 #define RT5682S_SAR_BUTDET_RST_NORM (0x1 << 13)
1338 #define RT5682S_SAR_BUTDET_RST (0x0 << 13)
1339 #define RT5682S_SAR_POW_MASK (0x1 << 12)
1340 #define RT5682S_SAR_POW_EN (0x1 << 12)
1341 #define RT5682S_SAR_POW_DIS (0x0 << 12)
1342 #define RT5682S_SAR_RST_MASK (0x1 << 11)
1343 #define RT5682S_SAR_RST_NORMAL (0x1 << 11)
1344 #define RT5682S_SAR_RST (0x0 << 11)
1345 #define RT5682S_SAR_BYPASS_MASK (0x1 << 10)
1346 #define RT5682S_SAR_BYPASS_EN (0x1 << 10)
1347 #define RT5682S_SAR_BYPASS_DIS (0x0 << 10)
1348 #define RT5682S_SAR_SEL_MB1_2_MASK (0x3 << 8)
1350 #define RT5682S_SAR_SEL_MODE_MASK (0x1 << 7)
1351 #define RT5682S_SAR_SEL_MODE_CMP (0x1 << 7)
1352 #define RT5682S_SAR_SEL_MODE_ADC (0x0 << 7)
1353 #define RT5682S_SAR_SEL_MB1_2_CTL_MASK (0x1 << 5)
1354 #define RT5682S_SAR_SEL_MB1_2_AUTO (0x1 << 5)
1355 #define RT5682S_SAR_SEL_MB1_2_MANU (0x0 << 5)
1356 #define RT5682S_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1357 #define RT5682S_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1358 #define RT5682S_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1360 /* SAR ADC Inline Command Control 2 (0x0211) */
1361 #define RT5682S_SAR_ADC_PSV_MASK (0x1 << 4)
1362 #define RT5682S_SAR_ADC_PSV_ENTRY (0x1 << 4)
1365 /* SAR ADC Inline Command Control 13 (0x021c) */
1366 #define RT5682S_SAR_SOUR_MASK (0x3f)
1367 #define RT5682S_SAR_SOUR_BTN (0x3f)
1368 #define RT5682S_SAR_SOUR_TYPE (0x0)
1370 /* Headphone Amp Detection Control 1 (0x3b00) */
1371 #define RT5682S_CP_SW_SIZE_MASK (0x7 << 4)
1372 #define RT5682S_CP_SW_SIZE_L (0x4 << 4)
1373 #define RT5682S_CP_SW_SIZE_M (0x2 << 4)
1374 #define RT5682S_CP_SW_SIZE_S (0x1 << 4)
1410 RT5682S_DA_STEREO1_FILTER = 0x1,
1411 RT5682S_AD_STEREO1_FILTER = (0x1 << 1),