Lines Matching +full:adc +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
26 #include <sound/soc-dapm.h>
59 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
748 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
749 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
784 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
787 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
790 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
793 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
796 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
806 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
812 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
816 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
817 if (!rt5682->is_sdw) in rt5682_reset()
818 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
823 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
846 return -EINVAL; in rt5682_sel_asrc_clk_src()
872 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); in rt5682_button_detect()
893 if (rt5682->is_sdw) in rt5682_enable_push_button_irq()
917 * rt5682_headset_detect - Detect headset.
928 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_headset_detect()
965 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_headset_detect()
971 rt5682->jack_type = SND_JACK_HEADPHONE; in rt5682_headset_detect()
1004 rt5682->jack_type = 0; in rt5682_headset_detect()
1007 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type); in rt5682_headset_detect()
1008 return rt5682->jack_type; in rt5682_headset_detect()
1016 rt5682->hs_jack = hs_jack; in rt5682_set_jack_detect()
1019 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1021 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1023 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_set_jack_detect()
1028 if (!rt5682->is_sdw) { in rt5682_set_jack_detect()
1029 switch (rt5682->pdata.jd_src) { in rt5682_set_jack_detect()
1044 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1, in rt5682_set_jack_detect()
1046 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1050 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2, in rt5682_set_jack_detect()
1052 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1055 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4, in rt5682_set_jack_detect()
1056 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1057 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1058 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5, in rt5682_set_jack_detect()
1059 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1060 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1061 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6, in rt5682_set_jack_detect()
1062 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1063 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1064 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7, in rt5682_set_jack_detect()
1065 0x7f7f, (rt5682->pdata.btndet_delay << 8 | in rt5682_set_jack_detect()
1066 rt5682->pdata.btndet_delay)); in rt5682_set_jack_detect()
1068 &rt5682->jack_detect_work, in rt5682_set_jack_detect()
1073 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2, in rt5682_set_jack_detect()
1075 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL, in rt5682_set_jack_detect()
1080 dev_warn(component->dev, "Wrong JD source\n"); in rt5682_set_jack_detect()
1095 if (!rt5682->component || !rt5682->component->card || in rt5682_jack_detect_handler()
1096 !rt5682->component->card->instantiated) { in rt5682_jack_detect_handler()
1099 &rt5682->jack_detect_work, msecs_to_jiffies(15)); in rt5682_jack_detect_handler()
1103 if (rt5682->is_sdw) { in rt5682_jack_detect_handler()
1104 if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) { in rt5682_jack_detect_handler()
1105 dev_dbg(&rt5682->slave->dev, in rt5682_jack_detect_handler()
1112 dapm = snd_soc_component_get_dapm(rt5682->component); in rt5682_jack_detect_handler()
1115 mutex_lock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1117 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL) in rt5682_jack_detect_handler()
1121 if (rt5682->jack_type == 0) { in rt5682_jack_detect_handler()
1123 rt5682->jack_type = in rt5682_jack_detect_handler()
1124 rt5682_headset_detect(rt5682->component, 1); in rt5682_jack_detect_handler()
1125 rt5682->irq_work_delay_time = 0; in rt5682_jack_detect_handler()
1126 } else if ((rt5682->jack_type & SND_JACK_HEADSET) == in rt5682_jack_detect_handler()
1129 rt5682->jack_type = SND_JACK_HEADSET; in rt5682_jack_detect_handler()
1130 btn_type = rt5682_button_detect(rt5682->component); in rt5682_jack_detect_handler()
1142 rt5682->jack_type |= SND_JACK_BTN_0; in rt5682_jack_detect_handler()
1147 rt5682->jack_type |= SND_JACK_BTN_1; in rt5682_jack_detect_handler()
1152 rt5682->jack_type |= SND_JACK_BTN_2; in rt5682_jack_detect_handler()
1157 rt5682->jack_type |= SND_JACK_BTN_3; in rt5682_jack_detect_handler()
1162 dev_err(rt5682->component->dev, in rt5682_jack_detect_handler()
1170 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0); in rt5682_jack_detect_handler()
1171 rt5682->irq_work_delay_time = 50; in rt5682_jack_detect_handler()
1174 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_jack_detect_handler()
1177 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type, in rt5682_jack_detect_handler()
1182 if (!rt5682->is_sdw) { in rt5682_jack_detect_handler()
1183 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5682_jack_detect_handler()
1185 schedule_delayed_work(&rt5682->jd_check_work, 0); in rt5682_jack_detect_handler()
1187 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_jack_detect_handler()
1201 /* ADC Digital Volume Control */
1202 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1204 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1207 /* ADC Boost Volume Control */
1208 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1218 if (rt5682->sysclk < target) { in rt5682_div_sel()
1219 dev_err(rt5682->component->dev, in rt5682_div_sel()
1220 "sysclk rate %d is too low\n", rt5682->sysclk); in rt5682_div_sel()
1224 for (i = 0; i < size - 1; i++) { in rt5682_div_sel()
1225 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]); in rt5682_div_sel()
1226 if (target * div[i] == rt5682->sysclk) in rt5682_div_sel()
1228 if (target * div[i + 1] > rt5682->sysclk) { in rt5682_div_sel()
1229 dev_dbg(rt5682->component->dev, in rt5682_div_sel()
1231 rt5682->sysclk); in rt5682_div_sel()
1236 if (target * div[i] < rt5682->sysclk) in rt5682_div_sel()
1237 dev_err(rt5682->component->dev, in rt5682_div_sel()
1238 "sysclk rate %d is too high\n", rt5682->sysclk); in rt5682_div_sel()
1240 return size - 1; in rt5682_div_sel()
1244 * set_dmic_clk - Set parameter of dmic.
1257 snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1262 if (rt5682->pdata.dmic_clk_rate) in set_dmic_clk()
1263 dmic_clk_rate = rt5682->pdata.dmic_clk_rate; in set_dmic_clk()
1277 snd_soc_dapm_to_component(w->dapm); in set_filter_clk()
1283 if (rt5682->is_sdw) in set_filter_clk()
1288 if (w->shift == RT5682_PWR_ADC_S1F_BIT && in set_filter_clk()
1290 ref = 256 * rt5682->lrck[RT5682_AIF2]; in set_filter_clk()
1292 ref = 256 * rt5682->lrck[RT5682_AIF1]; in set_filter_clk()
1296 if (w->shift == RT5682_PWR_ADC_S1F_BIT) in set_filter_clk()
1306 if (rt5682->sysclk <= 12288000 * div_o[idx]) in set_filter_clk()
1322 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll1()
1337 snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll2()
1352 snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1354 switch (w->shift) { in is_using_asrc()
1393 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1400 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1427 /* MX-26 [13] [5] */
1429 "DAC MIX", "ADC"
1446 /* STO1 ADC Source */
1447 /* MX-26 [11:10] [3:2] */
1467 /* MX-26 [12] [4] */
1486 /* MX-79 [6:4] I2S1 ADC data location */
1503 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1506 /* MX-2B [4], MX-2B [0]*/
1537 snd_soc_dapm_to_component(w->dapm); in rt5682_hp_event()
1576 snd_soc_dapm_to_component(w->dapm); in set_dmic_power()
1580 if (rt5682->pdata.dmic_delay) in set_dmic_power()
1581 delay = rt5682->pdata.dmic_delay; in set_dmic_power()
1598 if (!rt5682->jack_type) { in set_dmic_power()
1599 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS")) in set_dmic_power()
1602 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2")) in set_dmic_power()
1616 snd_soc_dapm_to_component(w->dapm); in rt5682_set_verf()
1620 switch (w->shift) { in rt5682_set_verf()
1635 switch (w->shift) { in rt5682_set_verf()
1705 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1753 /* ADC Mux */
1754 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1756 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1758 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1760 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1762 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1764 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1766 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1769 /* ADC Mixer */
1770 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1773 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1776 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1780 /* ADC PGA */
1781 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1795 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1797 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1799 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1801 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1803 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1806 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1809 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1811 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1830 /* DAC channel Mux */
1892 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1893 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1894 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1900 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1902 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1903 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1904 {"ADC STO1 ASRC", NULL, "CLKDET"},
1930 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1931 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1932 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1933 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1935 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1936 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1937 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1938 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1940 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1941 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1942 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1943 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1945 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1946 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1947 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1949 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1950 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1951 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1953 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1954 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1956 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1957 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1958 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1959 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1960 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1961 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1962 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1963 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1964 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1965 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1966 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1967 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1968 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1969 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1970 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1971 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1973 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1974 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1975 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1976 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1977 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1979 {"AIF1TX", NULL, "ADCDAT Mux"},
1980 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1981 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1982 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1983 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1984 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1985 {"AIF2TX", NULL, "ADCDAT Mux"},
1989 {"SDWTX", NULL, "ADCDAT Mux"},
2007 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
2008 {"DAC L Mux", "SOUND", "SOUND DAC L"},
2009 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
2010 {"DAC R Mux", "SOUND", "SOUND DAC R"},
2012 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2013 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2014 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2015 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2060 struct snd_soc_component *component = dai->component; in rt5682_set_tdm_slot()
2086 return -EINVAL; in rt5682_set_tdm_slot()
2095 return -EINVAL; in rt5682_set_tdm_slot()
2115 return -EINVAL; in rt5682_set_tdm_slot()
2129 struct snd_soc_component *component = dai->component; in rt5682_hw_params()
2134 rt5682->lrck[dai->id] = params_rate(params); in rt5682_hw_params()
2135 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]); in rt5682_hw_params()
2139 dev_err(component->dev, "Unsupported frame size: %d\n", in rt5682_hw_params()
2141 return -EINVAL; in rt5682_hw_params()
2144 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5682_hw_params()
2145 rt5682->lrck[dai->id], pre_div, dai->id); in rt5682_hw_params()
2167 return -EINVAL; in rt5682_hw_params()
2170 switch (dai->id) { in rt5682_hw_params()
2174 if (rt5682->master[RT5682_AIF1]) { in rt5682_hw_params()
2179 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_hw_params()
2193 if (rt5682->master[RT5682_AIF2]) { in rt5682_hw_params()
2208 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_hw_params()
2209 return -EINVAL; in rt5682_hw_params()
2217 struct snd_soc_component *component = dai->component; in rt5682_set_dai_fmt()
2223 rt5682->master[dai->id] = 1; in rt5682_set_dai_fmt()
2226 rt5682->master[dai->id] = 0; in rt5682_set_dai_fmt()
2229 return -EINVAL; in rt5682_set_dai_fmt()
2240 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2243 return -EINVAL; in rt5682_set_dai_fmt()
2246 if (dai->id == RT5682_AIF1) in rt5682_set_dai_fmt()
2250 return -EINVAL; in rt5682_set_dai_fmt()
2253 return -EINVAL; in rt5682_set_dai_fmt()
2272 return -EINVAL; in rt5682_set_dai_fmt()
2275 switch (dai->id) { in rt5682_set_dai_fmt()
2283 tdm_ctrl | rt5682->master[dai->id]); in rt5682_set_dai_fmt()
2286 if (rt5682->master[dai->id] == 0) in rt5682_set_dai_fmt()
2293 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5682_set_dai_fmt()
2294 return -EINVAL; in rt5682_set_dai_fmt()
2305 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src) in rt5682_set_component_sysclk()
2326 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5682_set_component_sysclk()
2327 return -EINVAL; in rt5682_set_component_sysclk()
2332 if (rt5682->master[RT5682_AIF2]) { in rt5682_set_component_sysclk()
2338 rt5682->sysclk = freq; in rt5682_set_component_sysclk()
2339 rt5682->sysclk_src = clk_id; in rt5682_set_component_sysclk()
2341 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt5682_set_component_sysclk()
2356 if (source == rt5682->pll_src[pll_id] && in rt5682_set_component_pll()
2357 freq_in == rt5682->pll_in[pll_id] && in rt5682_set_component_pll()
2358 freq_out == rt5682->pll_out[pll_id]) in rt5682_set_component_pll()
2362 dev_dbg(component->dev, "PLL disabled\n"); in rt5682_set_component_pll()
2364 rt5682->pll_in[pll_id] = 0; in rt5682_set_component_pll()
2365 rt5682->pll_out[pll_id] = 0; in rt5682_set_component_pll()
2379 dev_err(component->dev, "Unknown PLL2 Source %d\n", in rt5682_set_component_pll()
2381 return -EINVAL; in rt5682_set_component_pll()
2391 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2395 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2403 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2407 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2447 dev_err(component->dev, "Unknown PLL1 Source %d\n", in rt5682_set_component_pll()
2449 return -EINVAL; in rt5682_set_component_pll()
2454 dev_err(component->dev, "Unsupported input clock %d\n", in rt5682_set_component_pll()
2459 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5682_set_component_pll()
2470 rt5682->pll_in[pll_id] = freq_in; in rt5682_set_component_pll()
2471 rt5682->pll_out[pll_id] = freq_out; in rt5682_set_component_pll()
2472 rt5682->pll_src[pll_id] = source; in rt5682_set_component_pll()
2479 struct snd_soc_component *component = dai->component; in rt5682_set_bclk1_ratio()
2482 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk1_ratio()
2502 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio); in rt5682_set_bclk1_ratio()
2503 return -EINVAL; in rt5682_set_bclk1_ratio()
2511 struct snd_soc_component *component = dai->component; in rt5682_set_bclk2_ratio()
2514 rt5682->bclk[dai->id] = ratio; in rt5682_set_bclk2_ratio()
2528 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio); in rt5682_set_bclk2_ratio()
2529 return -EINVAL; in rt5682_set_bclk2_ratio()
2542 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2544 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2550 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2554 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1, in rt5682_set_bias_level()
2556 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1, in rt5682_set_bias_level()
2573 if (!rt5682->master[RT5682_AIF1]) { in rt5682_clk_check()
2574 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n"); in rt5682_clk_check()
2589 return -EINVAL; in rt5682_wclk_prepare()
2591 component = rt5682->component; in rt5682_wclk_prepare()
2629 component = rt5682->component; in rt5682_wclk_unprepare()
2636 if (!rt5682->jack_type) in rt5682_wclk_unprepare()
2662 if (rt5682->lrck[RT5682_AIF1] != CLK_48 && in rt5682_wclk_recalc_rate()
2663 rt5682->lrck[RT5682_AIF1] != CLK_44) { in rt5682_wclk_recalc_rate()
2664 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_recalc_rate()
2669 return rt5682->lrck[RT5682_AIF1]; in rt5682_wclk_recalc_rate()
2681 return -EINVAL; in rt5682_wclk_round_rate()
2687 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n", in rt5682_wclk_round_rate()
2708 return -EINVAL; in rt5682_wclk_set_rate()
2710 component = rt5682->component; in rt5682_wclk_set_rate()
2721 dev_warn(rt5682->i2c_dev, in rt5682_wclk_set_rate()
2726 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n", in rt5682_wclk_set_rate()
2740 rt5682->lrck[RT5682_AIF1] = rate; in rt5682_wclk_set_rate()
2742 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate); in rt5682_wclk_set_rate()
2747 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT); in rt5682_wclk_set_rate()
2760 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk); in rt5682_bclk_recalc_rate()
2801 return -EINVAL; in rt5682_bclk_round_rate()
2826 return -EINVAL; in rt5682_bclk_set_rate()
2828 component = rt5682->component; in rt5682_bclk_set_rate()
2833 if (dai->id == RT5682_AIF1) in rt5682_bclk_set_rate()
2836 dev_err(rt5682->i2c_dev, "dai %d not found in component\n", in rt5682_bclk_set_rate()
2838 return -ENODEV; in rt5682_bclk_set_rate()
2858 struct device *dev = rt5682->i2c_dev; in rt5682_register_dai_clks()
2859 struct rt5682_platform_data *pdata = &rt5682->pdata; in rt5682_register_dai_clks()
2867 dai_clk_hw = &rt5682->dai_clks_hw[i]; in rt5682_register_dai_clks()
2872 if (rt5682->mclk) { in rt5682_register_dai_clks()
2873 parent = __clk_get_hw(rt5682->mclk); in rt5682_register_dai_clks()
2880 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]; in rt5682_register_dai_clks()
2886 return -EINVAL; in rt5682_register_dai_clks()
2889 init.name = pdata->dai_clk_names[i]; in rt5682_register_dai_clks()
2892 dai_clk_hw->init = &init; in rt5682_register_dai_clks()
2901 if (dev->of_node) { in rt5682_register_dai_clks()
2923 struct snd_soc_dapm_context *dapm = &component->dapm; in rt5682_probe()
2925 rt5682->component = component; in rt5682_probe()
2927 if (rt5682->is_sdw) { in rt5682_probe()
2928 slave = rt5682->slave; in rt5682_probe()
2930 &slave->initialization_complete, in rt5682_probe()
2933 dev_err(&slave->dev, "Initialization not complete, timed out\n"); in rt5682_probe()
2934 return -ETIMEDOUT; in rt5682_probe()
2957 if (rt5682->is_sdw) in rt5682_suspend()
2960 cancel_delayed_work_sync(&rt5682->jack_detect_work); in rt5682_suspend()
2961 cancel_delayed_work_sync(&rt5682->jd_check_work); in rt5682_suspend()
2962 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { in rt5682_suspend()
2981 /* enter SAR ADC power saving mode */ in rt5682_suspend()
2997 regcache_cache_only(rt5682->regmap, true); in rt5682_suspend()
2998 regcache_mark_dirty(rt5682->regmap); in rt5682_suspend()
3006 if (rt5682->is_sdw) in rt5682_resume()
3009 regcache_cache_only(rt5682->regmap, false); in rt5682_resume()
3010 regcache_sync(rt5682->regmap); in rt5682_resume()
3012 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) { in rt5682_resume()
3024 rt5682->jack_type = 0; in rt5682_resume()
3026 &rt5682->jack_detect_work, msecs_to_jiffies(0)); in rt5682_resume()
3073 device_property_read_u32(dev, "realtek,dmic1-data-pin", in rt5682_parse_dt()
3074 &rt5682->pdata.dmic1_data_pin); in rt5682_parse_dt()
3075 device_property_read_u32(dev, "realtek,dmic1-clk-pin", in rt5682_parse_dt()
3076 &rt5682->pdata.dmic1_clk_pin); in rt5682_parse_dt()
3077 device_property_read_u32(dev, "realtek,jd-src", in rt5682_parse_dt()
3078 &rt5682->pdata.jd_src); in rt5682_parse_dt()
3079 device_property_read_u32(dev, "realtek,btndet-delay", in rt5682_parse_dt()
3080 &rt5682->pdata.btndet_delay); in rt5682_parse_dt()
3081 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz", in rt5682_parse_dt()
3082 &rt5682->pdata.dmic_clk_rate); in rt5682_parse_dt()
3083 device_property_read_u32(dev, "realtek,dmic-delay-ms", in rt5682_parse_dt()
3084 &rt5682->pdata.dmic_delay); in rt5682_parse_dt()
3086 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node, in rt5682_parse_dt()
3087 "realtek,ldo1-en-gpios", 0); in rt5682_parse_dt()
3089 if (device_property_read_string_array(dev, "clock-output-names", in rt5682_parse_dt()
3090 rt5682->pdata.dai_clk_names, in rt5682_parse_dt()
3093 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX], in rt5682_parse_dt()
3094 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]); in rt5682_parse_dt()
3096 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev, in rt5682_parse_dt()
3097 "realtek,dmic-clk-driving-high"); in rt5682_parse_dt()
3107 mutex_lock(&rt5682->calibrate_mutex); in rt5682_calibrate()
3110 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f); in rt5682_calibrate()
3111 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af); in rt5682_calibrate()
3113 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af); in rt5682_calibrate()
3114 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300); in rt5682_calibrate()
3115 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000); in rt5682_calibrate()
3116 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100); in rt5682_calibrate()
3117 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800); in rt5682_calibrate()
3118 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000); in rt5682_calibrate()
3119 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005); in rt5682_calibrate()
3120 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c); in rt5682_calibrate()
3121 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d); in rt5682_calibrate()
3122 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321); in rt5682_calibrate()
3123 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004); in rt5682_calibrate()
3124 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3125 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1); in rt5682_calibrate()
3126 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311); in rt5682_calibrate()
3127 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00); in rt5682_calibrate()
3129 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00); in rt5682_calibrate()
3132 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value); in rt5682_calibrate()
3140 dev_err(rt5682->component->dev, "HP Calibration Failure\n"); in rt5682_calibrate()
3143 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f); in rt5682_calibrate()
3144 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080); in rt5682_calibrate()
3145 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000); in rt5682_calibrate()
3146 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000); in rt5682_calibrate()
3147 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000); in rt5682_calibrate()
3148 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005); in rt5682_calibrate()
3149 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4); in rt5682_calibrate()
3150 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c); in rt5682_calibrate()
3152 mutex_unlock(&rt5682->calibrate_mutex); in rt5682_calibrate()