Lines Matching +full:tdm +full:- +full:data +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
14 #include <linux/delay.h>
31 #include <sound/soc-dapm.h>
37 #include "rt5677-spi.h"
554 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
555 * @rt5677: Private Data.
557 * @value: Address data.
565 struct snd_soc_component *component = rt5677->component; in rt5677_dsp_mode_i2c_write_addr()
568 mutex_lock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_write_addr()
570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, in rt5677_dsp_mode_i2c_write_addr()
573 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, in rt5677_dsp_mode_i2c_write_addr()
580 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, in rt5677_dsp_mode_i2c_write_addr()
587 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, in rt5677_dsp_mode_i2c_write_addr()
594 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
598 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, in rt5677_dsp_mode_i2c_write_addr()
601 dev_err(component->dev, "Failed to set op code value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
606 mutex_unlock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_write_addr()
612 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
613 * @rt5677: Private Data.
615 * @value: Address data.
623 struct snd_soc_component *component = rt5677->component; in rt5677_dsp_mode_i2c_read_addr()
627 mutex_lock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_read_addr()
629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, in rt5677_dsp_mode_i2c_read_addr()
632 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, in rt5677_dsp_mode_i2c_read_addr()
639 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
643 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, in rt5677_dsp_mode_i2c_read_addr()
646 dev_err(component->dev, "Failed to set op code value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
650 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); in rt5677_dsp_mode_i2c_read_addr()
651 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); in rt5677_dsp_mode_i2c_read_addr()
655 mutex_unlock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_read_addr()
661 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
662 * @rt5677: Private Data.
664 * @value: Register data.
677 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
678 * @rt5677: Private Data
680 * @value: Register data.
699 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_set_dsp_mode()
701 rt5677->is_dsp_mode = true; in rt5677_set_dsp_mode()
703 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_set_dsp_mode()
705 rt5677->is_dsp_mode = false; in rt5677_set_dsp_mode()
712 snd_soc_component_get_dapm(rt5677->component); in rt5677_set_vad_source()
721 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, in rt5677_set_vad_source()
725 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_set_vad_source()
729 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, in rt5677_set_vad_source()
733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); in rt5677_set_vad_source()
735 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); in rt5677_set_vad_source()
740 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, in rt5677_set_vad_source()
743 /* Minimum frame level within a pre-determined duration = 32 frames in rt5677_set_vad_source()
745 * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable in rt5677_set_vad_source()
746 * SAD Buffer Over-Writing = enable in rt5677_set_vad_source()
753 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, in rt5677_set_vad_source()
759 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it in rt5677_set_vad_source()
766 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, in rt5677_set_vad_source()
772 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_vad_source()
779 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_vad_source()
789 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, in rt5677_set_vad_source()
802 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_set_vad_source()
816 struct snd_soc_component *component = rt5677->component; in rt5677_parse_and_load_dsp()
823 return -ENOMEM; in rt5677_parse_and_load_dsp()
829 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) in rt5677_parse_and_load_dsp()
830 dev_err(component->dev, "Wrong ELF header prefix\n"); in rt5677_parse_and_load_dsp()
831 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) in rt5677_parse_and_load_dsp()
832 dev_err(component->dev, "Wrong Elf header size\n"); in rt5677_parse_and_load_dsp()
833 if (elf_hdr->e_machine != EM_XTENSA) in rt5677_parse_and_load_dsp()
834 dev_err(component->dev, "Wrong DSP code file\n"); in rt5677_parse_and_load_dsp()
836 if (len < elf_hdr->e_phoff) in rt5677_parse_and_load_dsp()
837 return -ENOMEM; in rt5677_parse_and_load_dsp()
838 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); in rt5677_parse_and_load_dsp()
839 for (i = 0; i < elf_hdr->e_phnum; i++) { in rt5677_parse_and_load_dsp()
841 if (pr_hdr->p_paddr && pr_hdr->p_filesz) { in rt5677_parse_and_load_dsp()
842 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", in rt5677_parse_and_load_dsp()
843 pr_hdr->p_filesz, pr_hdr->p_paddr); in rt5677_parse_and_load_dsp()
845 ret = rt5677_spi_write(pr_hdr->p_paddr, in rt5677_parse_and_load_dsp()
846 buf + pr_hdr->p_offset, in rt5677_parse_and_load_dsp()
847 pr_hdr->p_filesz); in rt5677_parse_and_load_dsp()
849 dev_err(component->dev, "Load firmware failed %d\n", in rt5677_parse_and_load_dsp()
860 struct device *dev = rt5677->component->dev; in rt5677_load_dsp_from_file()
869 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); in rt5677_load_dsp_from_file()
871 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); in rt5677_load_dsp_from_file()
879 rt5677->dsp_vad_en_request = on; in rt5677_set_dsp_vad()
880 rt5677->dsp_vad_en = on; in rt5677_set_dsp_vad()
883 return -ENXIO; in rt5677_set_dsp_vad()
885 schedule_delayed_work(&rt5677->dsp_work, 0); in rt5677_set_dsp_vad()
894 bool enable = rt5677->dsp_vad_en; in rt5677_dsp_work()
898 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", in rt5677_dsp_work()
919 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); in rt5677_dsp_work()
925 dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); in rt5677_dsp_work()
940 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_dsp_work()
946 mutex_lock(&rt5677->irq_lock); in rt5677_dsp_work()
948 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_dsp_work()
954 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); in rt5677_dsp_work()
957 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, in rt5677_dsp_work()
960 mutex_unlock(&rt5677->irq_lock); in rt5677_dsp_work()
964 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
965 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
967 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
986 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request; in rt5677_dsp_vad_get()
996 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]); in rt5677_dsp_vad_put()
1078 * set_dmic_clk - Set parameter of dmic.
1090 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1094 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, in set_dmic_clk()
1098 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1100 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, in set_dmic_clk()
1108 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in is_sys_clk_from_pll()
1112 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); in is_sys_clk_from_pll()
1123 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in is_using_asrc()
1127 if (source->reg == RT5677_ASRC_1) { in is_using_asrc()
1128 switch (source->shift) { in is_using_asrc()
1149 switch (source->shift) { in is_using_asrc()
1191 regmap_read(rt5677->regmap, reg, &val); in is_using_asrc()
1206 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in can_use_asrc()
1209 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) in can_use_asrc()
1216 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1257 return -EINVAL; in rt5677_sel_asrc_clk_src()
1280 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, in rt5677_sel_asrc_clk_src()
1309 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, in rt5677_sel_asrc_clk_src()
1338 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, in rt5677_sel_asrc_clk_src()
1355 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, in rt5677_sel_asrc_clk_src()
1372 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, in rt5677_sel_asrc_clk_src()
1379 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1385 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1391 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1397 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1401 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, in rt5677_sel_asrc_clk_src()
1411 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in rt5677_dmic_use_asrc()
1415 switch (source->shift) { in rt5677_dmic_use_asrc()
1417 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1423 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1429 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1435 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1441 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); in rt5677_dmic_use_asrc()
1447 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); in rt5677_dmic_use_asrc()
1740 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1753 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1766 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1791 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1816 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1841 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1881 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1907 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1954 /* Stereo2 ADC Source */ /* MX-26 [0] */
1966 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1992 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
2004 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
2016 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
2028 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
2040 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
2053 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
2065 /* InBound0/1 Source */ /* MX-A3 [14:12] */
2078 /* InBound2/3 Source */ /* MX-A3 [10:8] */
2091 /* InBound4/5 Source */ /* MX-A3 [6:4] */
2104 /* InBound6 Source */ /* MX-A3 [2:0] */
2117 /* InBound7 Source */ /* MX-A4 [14:12] */
2130 /* InBound8 Source */ /* MX-A4 [10:8] */
2143 /* InBound9 Source */ /* MX-A4 [6:4] */
2156 /* VAD Source */ /* MX-9F [6:4] */
2169 /* Sidetone Source */ /* MX-13 [11:9] */
2181 /* DAC1/2 Source */ /* MX-15 [1:0] */
2193 /* DAC3 Source */ /* MX-15 [5:4] */
2205 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2238 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2264 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2290 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2316 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2342 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2362 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2423 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2434 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2436 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2447 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2449 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2450 MX-3F[14:12][10:8][6:4][2:0]
2451 MX-43[14:12][10:8][6:4][2:0]
2452 MX-44[14:12][10:8][6:4][2:0] */
2462 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2469 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2476 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2483 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2490 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2497 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2504 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2511 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2518 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2525 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2532 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2539 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2546 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2553 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2560 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2567 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2572 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_bst1_event()
2577 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2582 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2596 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_bst2_event()
2601 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2606 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2620 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_pll1_event()
2625 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); in rt5677_set_pll1_event()
2629 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); in rt5677_set_pll1_event()
2642 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_pll2_event()
2647 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); in rt5677_set_pll2_event()
2651 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); in rt5677_set_pll2_event()
2664 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_micbias1_event()
2669 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2676 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2691 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_if1_adc_tdm_event()
2697 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); in rt5677_if1_adc_tdm_event()
2699 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, in rt5677_if1_adc_tdm_event()
2714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_if2_adc_tdm_event()
2720 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); in rt5677_if2_adc_tdm_event()
2722 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, in rt5677_if2_adc_tdm_event()
2737 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_vref_event()
2743 !rt5677->is_vref_slow) { in rt5677_vref_event()
2745 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_vref_event()
2748 rt5677->is_vref_slow = true; in rt5677_vref_event()
3107 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
3126 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
3613 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3614 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3615 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3616 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3617 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3618 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3619 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3620 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3623 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3665 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3666 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3667 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3668 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3669 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3670 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3671 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3672 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3675 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3735 * there is an active path going from system playback -> "DAC1 FS" ->
3736 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses
4292 struct snd_soc_component *component = dai->component; in rt5677_hw_params()
4297 rt5677->lrck[dai->id] = params_rate(params); in rt5677_hw_params()
4298 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); in rt5677_hw_params()
4300 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", in rt5677_hw_params()
4301 rt5677->sysclk, rt5677->lrck[dai->id]); in rt5677_hw_params()
4302 return -EINVAL; in rt5677_hw_params()
4306 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5677_hw_params()
4307 return -EINVAL; in rt5677_hw_params()
4310 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); in rt5677_hw_params()
4312 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", in rt5677_hw_params()
4313 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); in rt5677_hw_params()
4314 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", in rt5677_hw_params()
4315 bclk_ms, pre_div, dai->id); in rt5677_hw_params()
4330 return -EINVAL; in rt5677_hw_params()
4333 switch (dai->id) { in rt5677_hw_params()
4337 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, in rt5677_hw_params()
4339 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4345 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, in rt5677_hw_params()
4347 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4354 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, in rt5677_hw_params()
4356 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4363 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, in rt5677_hw_params()
4365 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4377 struct snd_soc_component *component = dai->component; in rt5677_set_dai_fmt()
4383 rt5677->master[dai->id] = 1; in rt5677_set_dai_fmt()
4387 rt5677->master[dai->id] = 0; in rt5677_set_dai_fmt()
4390 return -EINVAL; in rt5677_set_dai_fmt()
4400 return -EINVAL; in rt5677_set_dai_fmt()
4416 return -EINVAL; in rt5677_set_dai_fmt()
4419 switch (dai->id) { in rt5677_set_dai_fmt()
4421 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, in rt5677_set_dai_fmt()
4426 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, in rt5677_set_dai_fmt()
4431 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, in rt5677_set_dai_fmt()
4436 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, in rt5677_set_dai_fmt()
4451 struct snd_soc_component *component = dai->component; in rt5677_set_dai_sysclk()
4455 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) in rt5677_set_dai_sysclk()
4469 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5677_set_dai_sysclk()
4470 return -EINVAL; in rt5677_set_dai_sysclk()
4472 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_sysclk()
4474 rt5677->sysclk = freq; in rt5677_set_dai_sysclk()
4475 rt5677->sysclk_src = clk_id; in rt5677_set_dai_sysclk()
4477 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); in rt5677_set_dai_sysclk()
4483 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4496 return -EINVAL; in rt5677_pll_calc()
4504 struct snd_soc_component *component = dai->component; in rt5677_set_dai_pll()
4509 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && in rt5677_set_dai_pll()
4510 freq_out == rt5677->pll_out) in rt5677_set_dai_pll()
4514 dev_dbg(component->dev, "PLL disabled\n"); in rt5677_set_dai_pll()
4516 rt5677->pll_in = 0; in rt5677_set_dai_pll()
4517 rt5677->pll_out = 0; in rt5677_set_dai_pll()
4518 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4525 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4532 switch (dai->id) { in rt5677_set_dai_pll()
4534 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4538 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4542 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4546 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4554 dev_err(component->dev, "Unknown PLL source %d\n", source); in rt5677_set_dai_pll()
4555 return -EINVAL; in rt5677_set_dai_pll()
4560 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5677_set_dai_pll()
4564 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", in rt5677_set_dai_pll()
4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, in rt5677_set_dai_pll()
4570 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, in rt5677_set_dai_pll()
4574 rt5677->pll_in = freq_in; in rt5677_set_dai_pll()
4575 rt5677->pll_out = freq_out; in rt5677_set_dai_pll()
4576 rt5677->pll_src = source; in rt5677_set_dai_pll()
4584 struct snd_soc_component *component = dai->component; in rt5677_set_tdm_slot()
4624 switch (dai->id) { in rt5677_set_tdm_slot()
4626 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, in rt5677_set_tdm_slot()
4628 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, in rt5677_set_tdm_slot()
4632 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, in rt5677_set_tdm_slot()
4634 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, in rt5677_set_tdm_slot()
4658 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4662 regmap_update_bits(rt5677->regmap, in rt5677_set_bias_level()
4665 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4671 rt5677->is_vref_slow = false; in rt5677_set_bias_level()
4672 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_bias_level()
4674 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_set_bias_level()
4681 rt5677->dsp_vad_en_request) { in rt5677_set_bias_level()
4682 /* Re-enable the DSP if it was turned off at suspend */ in rt5677_set_bias_level()
4683 rt5677->dsp_vad_en = true; in rt5677_set_bias_level()
4684 /* The delay is to wait for MCLK */ in rt5677_set_bias_level()
4685 schedule_delayed_work(&rt5677->dsp_work, in rt5677_set_bias_level()
4691 flush_delayed_work(&rt5677->dsp_work); in rt5677_set_bias_level()
4692 if (rt5677->is_dsp_mode) { in rt5677_set_bias_level()
4694 rt5677->dsp_vad_en = false; in rt5677_set_bias_level()
4695 schedule_delayed_work(&rt5677->dsp_work, 0); in rt5677_set_bias_level()
4696 flush_delayed_work(&rt5677->dsp_work); in rt5677_set_bias_level()
4699 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); in rt5677_set_bias_level()
4700 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); in rt5677_set_bias_level()
4701 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4704 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_bias_level()
4706 regmap_update_bits(rt5677->regmap, in rt5677_set_bias_level()
4709 if (rt5677->dsp_vad_en) in rt5677_set_bias_level()
4727 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_gpio_set()
4732 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, in rt5677_gpio_set()
4748 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_gpio_direction_out()
4754 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, in rt5677_gpio_direction_out()
4771 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); in rt5677_gpio_get()
4784 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_gpio_direction_in()
4789 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, in rt5677_gpio_direction_in()
4801 * 0 - floating
4802 * 1 - pull down
4803 * 2 - pull up
4812 shift = 2 * (1 - offset); in rt5677_gpio_config()
4813 regmap_update_bits(rt5677->regmap, in rt5677_gpio_config()
4820 shift = 2 * (9 - offset); in rt5677_gpio_config()
4821 regmap_update_bits(rt5677->regmap, in rt5677_gpio_config()
4837 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || in rt5677_to_irq()
4838 (rt5677->pdata.jd1_gpio == 2 && in rt5677_to_irq()
4840 (rt5677->pdata.jd1_gpio == 3 && in rt5677_to_irq()
4843 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || in rt5677_to_irq()
4844 (rt5677->pdata.jd2_gpio == 2 && in rt5677_to_irq()
4846 (rt5677->pdata.jd2_gpio == 3 && in rt5677_to_irq()
4849 } else if ((rt5677->pdata.jd3_gpio == 1 && in rt5677_to_irq()
4851 (rt5677->pdata.jd3_gpio == 2 && in rt5677_to_irq()
4853 (rt5677->pdata.jd3_gpio == 3 && in rt5677_to_irq()
4857 return -ENXIO; in rt5677_to_irq()
4860 return irq_create_mapping(rt5677->domain, irq); in rt5677_to_irq()
4879 rt5677->gpio_chip = rt5677_template_chip; in rt5677_init_gpio()
4880 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; in rt5677_init_gpio()
4881 rt5677->gpio_chip.parent = &i2c->dev; in rt5677_init_gpio()
4882 rt5677->gpio_chip.base = -1; in rt5677_init_gpio()
4884 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); in rt5677_init_gpio()
4886 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); in rt5677_init_gpio()
4893 gpiochip_remove(&rt5677->gpio_chip); in rt5677_free_gpio()
4916 rt5677->component = component; in rt5677_probe()
4918 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { in rt5677_probe()
4930 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_probe()
4932 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, in rt5677_probe()
4936 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); in rt5677_probe()
4938 mutex_init(&rt5677->dsp_cmd_lock); in rt5677_probe()
4939 mutex_init(&rt5677->dsp_pri_lock); in rt5677_probe()
4948 cancel_delayed_work_sync(&rt5677->dsp_work); in rt5677_remove()
4950 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_remove()
4951 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); in rt5677_remove()
4952 gpiod_set_value_cansleep(rt5677->reset_pin, 1); in rt5677_remove()
4960 if (rt5677->irq) { in rt5677_suspend()
4961 cancel_delayed_work_sync(&rt5677->resume_irq_check); in rt5677_suspend()
4962 disable_irq(rt5677->irq); in rt5677_suspend()
4965 if (!rt5677->dsp_vad_en) { in rt5677_suspend()
4966 regcache_cache_only(rt5677->regmap, true); in rt5677_suspend()
4967 regcache_mark_dirty(rt5677->regmap); in rt5677_suspend()
4969 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); in rt5677_suspend()
4970 gpiod_set_value_cansleep(rt5677->reset_pin, 1); in rt5677_suspend()
4980 if (!rt5677->dsp_vad_en) { in rt5677_resume()
4981 rt5677->pll_src = 0; in rt5677_resume()
4982 rt5677->pll_in = 0; in rt5677_resume()
4983 rt5677->pll_out = 0; in rt5677_resume()
4984 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); in rt5677_resume()
4985 gpiod_set_value_cansleep(rt5677->reset_pin, 0); in rt5677_resume()
4986 if (rt5677->pow_ldo2 || rt5677->reset_pin) in rt5677_resume()
4989 regcache_cache_only(rt5677->regmap, false); in rt5677_resume()
4990 regcache_sync(rt5677->regmap); in rt5677_resume()
4993 if (rt5677->irq) { in rt5677_resume()
4994 enable_irq(rt5677->irq); in rt5677_resume()
4995 schedule_delayed_work(&rt5677->resume_irq_check, 0); in rt5677_resume()
5010 if (rt5677->is_dsp_mode) { in rt5677_read()
5012 mutex_lock(&rt5677->dsp_pri_lock); in rt5677_read()
5016 mutex_unlock(&rt5677->dsp_pri_lock); in rt5677_read()
5021 regmap_read(rt5677->regmap_physical, reg, val); in rt5677_read()
5032 if (rt5677->is_dsp_mode) { in rt5677_write()
5034 mutex_lock(&rt5677->dsp_pri_lock); in rt5677_write()
5039 mutex_unlock(&rt5677->dsp_pri_lock); in rt5677_write()
5044 regmap_write(rt5677->regmap_physical, reg, val); in rt5677_write()
5069 .name = "rt5677-aif1",
5088 .name = "rt5677-aif2",
5107 .name = "rt5677-aif3",
5126 .name = "rt5677-aif4",
5145 .name = "rt5677-slimbus",
5164 .name = "rt5677-dspbuffer",
5228 { .compatible = "realtek,rt5677", .data = (const void *)RT5677 },
5244 rt5677->pdata.in1_diff = in rt5677_read_device_properties()
5246 device_property_read_bool(dev, "realtek,in1-differential"); in rt5677_read_device_properties()
5248 rt5677->pdata.in2_diff = in rt5677_read_device_properties()
5250 device_property_read_bool(dev, "realtek,in2-differential"); in rt5677_read_device_properties()
5252 rt5677->pdata.lout1_diff = in rt5677_read_device_properties()
5254 device_property_read_bool(dev, "realtek,lout1-differential"); in rt5677_read_device_properties()
5256 rt5677->pdata.lout2_diff = in rt5677_read_device_properties()
5258 device_property_read_bool(dev, "realtek,lout2-differential"); in rt5677_read_device_properties()
5260 rt5677->pdata.lout3_diff = in rt5677_read_device_properties()
5262 device_property_read_bool(dev, "realtek,lout3-differential"); in rt5677_read_device_properties()
5264 device_property_read_u8_array(dev, "realtek,gpio-config", in rt5677_read_device_properties()
5265 rt5677->pdata.gpio_config, in rt5677_read_device_properties()
5270 rt5677->pdata.dmic2_clk_pin = val; in rt5677_read_device_properties()
5273 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) in rt5677_read_device_properties()
5274 rt5677->pdata.jd1_gpio = val; in rt5677_read_device_properties()
5277 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) in rt5677_read_device_properties()
5278 rt5677->pdata.jd2_gpio = val; in rt5677_read_device_properties()
5281 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) in rt5677_read_device_properties()
5282 rt5677->pdata.jd3_gpio = val; in rt5677_read_device_properties()
5313 if (!rt5677->is_dsp_mode) in rt5677_check_hotword()
5316 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) in rt5677_check_hotword()
5324 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, in rt5677_check_hotword()
5331 static irqreturn_t rt5677_irq(int unused, void *data) in rt5677_irq() argument
5333 struct rt5677_priv *rt5677 = data; in rt5677_irq()
5337 mutex_lock(&rt5677->irq_lock); in rt5677_irq()
5355 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); in rt5677_irq()
5357 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", in rt5677_irq()
5366 virq = irq_find_mapping(rt5677->domain, i); in rt5677_irq()
5385 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); in rt5677_irq()
5387 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", in rt5677_irq()
5394 mutex_unlock(&rt5677->irq_lock); in rt5677_irq()
5417 * scheduled by soc-jack may run and read wrong jack gpio values, since in rt5677_resume_irq_check()
5423 mutex_lock(&rt5677->irq_lock); in rt5677_resume_irq_check()
5425 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { in rt5677_resume_irq_check()
5426 virq = irq_find_mapping(rt5677->domain, i); in rt5677_resume_irq_check()
5431 mutex_unlock(&rt5677->irq_lock); in rt5677_resume_irq_check()
5434 static void rt5677_irq_bus_lock(struct irq_data *data) in rt5677_irq_bus_lock() argument
5436 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); in rt5677_irq_bus_lock()
5438 mutex_lock(&rt5677->irq_lock); in rt5677_irq_bus_lock()
5441 static void rt5677_irq_bus_sync_unlock(struct irq_data *data) in rt5677_irq_bus_sync_unlock() argument
5443 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); in rt5677_irq_bus_sync_unlock()
5446 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, in rt5677_irq_bus_sync_unlock()
5448 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); in rt5677_irq_bus_sync_unlock()
5449 mutex_unlock(&rt5677->irq_lock); in rt5677_irq_bus_sync_unlock()
5452 static void rt5677_irq_enable(struct irq_data *data) in rt5677_irq_enable() argument
5454 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); in rt5677_irq_enable()
5456 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; in rt5677_irq_enable()
5459 static void rt5677_irq_disable(struct irq_data *data) in rt5677_irq_disable() argument
5461 struct rt5677_priv *rt5677 = irq_data_get_irq_chip_data(data); in rt5677_irq_disable()
5463 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; in rt5677_irq_disable()
5477 struct rt5677_priv *rt5677 = h->host_data; in rt5677_irq_map()
5498 if (!rt5677->pdata.jd1_gpio && in rt5677_init_irq()
5499 !rt5677->pdata.jd2_gpio && in rt5677_init_irq()
5500 !rt5677->pdata.jd3_gpio) in rt5677_init_irq()
5503 if (!i2c->irq) { in rt5677_init_irq()
5504 dev_err(&i2c->dev, "No interrupt specified\n"); in rt5677_init_irq()
5505 return -EINVAL; in rt5677_init_irq()
5508 mutex_init(&rt5677->irq_lock); in rt5677_init_irq()
5509 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check); in rt5677_init_irq()
5516 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_init_irq()
5520 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); in rt5677_init_irq()
5522 /* Select and enable jack detection sources per platform data */ in rt5677_init_irq()
5523 if (rt5677->pdata.jd1_gpio) { in rt5677_init_irq()
5525 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; in rt5677_init_irq()
5527 if (rt5677->pdata.jd2_gpio) { in rt5677_init_irq()
5529 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; in rt5677_init_irq()
5531 if (rt5677->pdata.jd3_gpio) { in rt5677_init_irq()
5533 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; in rt5677_init_irq()
5535 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); in rt5677_init_irq()
5538 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, in rt5677_init_irq()
5542 rt5677->domain = irq_domain_add_linear(i2c->dev.of_node, in rt5677_init_irq()
5544 if (!rt5677->domain) { in rt5677_init_irq()
5545 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); in rt5677_init_irq()
5546 return -ENOMEM; in rt5677_init_irq()
5549 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, in rt5677_init_irq()
5553 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); in rt5677_init_irq()
5555 rt5677->irq = i2c->irq; in rt5677_init_irq()
5566 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), in rt5677_i2c_probe()
5569 return -ENOMEM; in rt5677_i2c_probe()
5571 rt5677->dev = &i2c->dev; in rt5677_i2c_probe()
5572 rt5677->set_dsp_vad = rt5677_set_dsp_vad; in rt5677_i2c_probe()
5573 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); in rt5677_i2c_probe()
5576 if (i2c->dev.of_node) { in rt5677_i2c_probe()
5579 match_id = of_match_device(rt5677_of_match, &i2c->dev); in rt5677_i2c_probe()
5581 rt5677->type = (enum rt5677_type)match_id->data; in rt5677_i2c_probe()
5582 } else if (ACPI_HANDLE(&i2c->dev)) { in rt5677_i2c_probe()
5585 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev); in rt5677_i2c_probe()
5587 rt5677->type = (enum rt5677_type)acpi_id->driver_data; in rt5677_i2c_probe()
5589 return -EINVAL; in rt5677_i2c_probe()
5592 rt5677_read_device_properties(rt5677, &i2c->dev); in rt5677_i2c_probe()
5594 /* pow-ldo2 and reset are optional. The codec pins may be statically in rt5677_i2c_probe()
5598 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, in rt5677_i2c_probe()
5599 "realtek,pow-ldo2", GPIOD_OUT_HIGH); in rt5677_i2c_probe()
5600 if (IS_ERR(rt5677->pow_ldo2)) { in rt5677_i2c_probe()
5601 ret = PTR_ERR(rt5677->pow_ldo2); in rt5677_i2c_probe()
5602 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); in rt5677_i2c_probe()
5605 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, in rt5677_i2c_probe()
5607 if (IS_ERR(rt5677->reset_pin)) { in rt5677_i2c_probe()
5608 ret = PTR_ERR(rt5677->reset_pin); in rt5677_i2c_probe()
5609 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); in rt5677_i2c_probe()
5613 if (rt5677->pow_ldo2 || rt5677->reset_pin) { in rt5677_i2c_probe()
5621 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, in rt5677_i2c_probe()
5623 if (IS_ERR(rt5677->regmap_physical)) { in rt5677_i2c_probe()
5624 ret = PTR_ERR(rt5677->regmap_physical); in rt5677_i2c_probe()
5625 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5677_i2c_probe()
5630 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); in rt5677_i2c_probe()
5631 if (IS_ERR(rt5677->regmap)) { in rt5677_i2c_probe()
5632 ret = PTR_ERR(rt5677->regmap); in rt5677_i2c_probe()
5633 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5677_i2c_probe()
5638 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); in rt5677_i2c_probe()
5640 dev_err(&i2c->dev, in rt5677_i2c_probe()
5642 return -ENODEV; in rt5677_i2c_probe()
5645 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_i2c_probe()
5647 ret = regmap_register_patch(rt5677->regmap, init_list, in rt5677_i2c_probe()
5650 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); in rt5677_i2c_probe()
5652 if (rt5677->pdata.in1_diff) in rt5677_i2c_probe()
5653 regmap_update_bits(rt5677->regmap, RT5677_IN1, in rt5677_i2c_probe()
5656 if (rt5677->pdata.in2_diff) in rt5677_i2c_probe()
5657 regmap_update_bits(rt5677->regmap, RT5677_IN1, in rt5677_i2c_probe()
5660 if (rt5677->pdata.lout1_diff) in rt5677_i2c_probe()
5661 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5664 if (rt5677->pdata.lout2_diff) in rt5677_i2c_probe()
5665 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5668 if (rt5677->pdata.lout3_diff) in rt5677_i2c_probe()
5669 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5672 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { in rt5677_i2c_probe()
5673 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, in rt5677_i2c_probe()
5676 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_i2c_probe()
5681 if (rt5677->pdata.micbias1_vdd_3v3) in rt5677_i2c_probe()
5682 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, in rt5677_i2c_probe()
5689 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); in rt5677_i2c_probe()
5691 return devm_snd_soc_register_component(&i2c->dev, in rt5677_i2c_probe()