Lines Matching full:x1
431 #define RT5665_L_MUTE (0x1 << 15)
433 #define RT5665_VOL_L_MUTE (0x1 << 14)
435 #define RT5665_R_MUTE (0x1 << 7)
437 #define RT5665_VOL_R_MUTE (0x1 << 6)
455 #define RT5665_IN1_DF_MASK (0x1 << 15)
459 #define RT5665_IN2_DF_MASK (0x1 << 7)
465 #define RT5665_IN3_DF_MASK (0x1 << 15)
469 #define RT5665_IN4_DF_MASK (0x1 << 7)
481 #define RT5665_EMB_JD_EN (0x1 << 15)
483 #define RT5665_JD_MODE (0x1 << 13)
485 #define RT5665_POLA_EXT_JD_MASK (0x1 << 11)
486 #define RT5665_POLA_EXT_JD_LOW (0x1 << 11)
488 #define RT5665_EXT_JD_DIG (0x1 << 9)
489 #define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
490 #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
492 #define RT5665_VREF_POW_MASK (0x1 << 6)
494 #define RT5665_VREF_POW_REG (0x1 << 6)
495 #define RT5665_MB1_PATH_MASK (0x1 << 5)
496 #define RT5665_CTRL_MB1_REG (0x1 << 5)
498 #define RT5665_MB2_PATH_MASK (0x1 << 4)
499 #define RT5665_CTRL_MB2_REG (0x1 << 4)
501 #define RT5665_TRIG_JD_MASK (0x1 << 3)
502 #define RT5665_TRIG_JD_HIGH (0x1 << 3)
509 #define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
519 #define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
520 #define RT5665_CBJ_JD_TEST_MASK (0x1 << 6)
522 #define RT5665_CBJ_JD_TEST_MODE (0x1 << 6)
525 #define RT5665_SIL_DET_MASK (0x1 << 15)
527 #define RT5665_SIL_DET_EN (0x1 << 15)
530 #define RT5665_M_DAC2_L_VOL (0x1 << 13)
532 #define RT5665_M_DAC2_R_VOL (0x1 << 12)
542 #define RT5665_ST_EN (0x1 << 6)
558 #define RT5665_M_DAC3_L_VOL (0x1 << 13)
560 #define RT5665_M_DAC3_R_VOL (0x1 << 12)
598 #define RT5665_M_STO1_ADC_L1 (0x1 << 15)
600 #define RT5665_M_STO1_ADC_L2 (0x1 << 14)
602 #define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)
604 #define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)
606 #define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
610 #define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)
612 #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
614 #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
616 #define RT5665_M_STO1_ADC_R1 (0x1 << 7)
618 #define RT5665_M_STO1_ADC_R2 (0x1 << 6)
620 #define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5)
622 #define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4)
631 #define RT5665_M_MONO_ADC_L1 (0x1 << 15)
633 #define RT5665_M_MONO_ADC_L2 (0x1 << 14)
635 #define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)
637 #define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
641 #define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)
643 #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
645 #define RT5665_M_MONO_ADC_R1 (0x1 << 7)
647 #define RT5665_M_MONO_ADC_R2 (0x1 << 6)
649 #define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5)
651 #define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4)
655 #define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1)
657 #define RT5665_MONO_DMIC_R_SRC_MASK 0x1
661 #define RT5665_M_STO2_ADC_L1 (0x1 << 15)
664 #define RT5665_M_STO2_ADC_L2 (0x1 << 14)
666 #define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)
668 #define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)
670 #define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
674 #define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)
676 #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
678 #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
680 #define RT5665_M_STO2_ADC_R1 (0x1 << 7)
683 #define RT5665_M_STO2_ADC_R2 (0x1 << 6)
685 #define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5)
687 #define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4)
691 #define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1)
695 #define RT5665_M_ADCMIX_L (0x1 << 15)
697 #define RT5665_M_DAC1_L (0x1 << 14)
703 #define RT5665_M_ADCMIX_R (0x1 << 7)
705 #define RT5665_M_DAC1_R (0x1 << 6)
709 #define RT5665_M_DAC_L1_STO_L (0x1 << 15)
711 #define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14)
713 #define RT5665_M_DAC_R1_STO_L (0x1 << 13)
715 #define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
717 #define RT5665_M_DAC_L2_STO_L (0x1 << 11)
719 #define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10)
721 #define RT5665_M_DAC_R2_STO_L (0x1 << 9)
723 #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
725 #define RT5665_M_DAC_L1_STO_R (0x1 << 7)
727 #define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6)
729 #define RT5665_M_DAC_R1_STO_R (0x1 << 5)
731 #define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4)
733 #define RT5665_M_DAC_L2_STO_R (0x1 << 3)
735 #define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2)
737 #define RT5665_M_DAC_R2_STO_R (0x1 << 1)
739 #define RT5665_G_DAC_R2_STO_R_MASK (0x1)
743 #define RT5665_M_DAC_L1_MONO_L (0x1 << 15)
745 #define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14)
747 #define RT5665_M_DAC_R1_MONO_L (0x1 << 13)
749 #define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
751 #define RT5665_M_DAC_L2_MONO_L (0x1 << 11)
753 #define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10)
755 #define RT5665_M_DAC_R2_MONO_L (0x1 << 9)
757 #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
759 #define RT5665_M_DAC_L1_MONO_R (0x1 << 7)
761 #define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6)
763 #define RT5665_M_DAC_R1_MONO_R (0x1 << 5)
765 #define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4)
767 #define RT5665_M_DAC_L2_MONO_R (0x1 << 3)
769 #define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2)
771 #define RT5665_M_DAC_R2_MONO_R (0x1 << 1)
773 #define RT5665_G_DAC_R2_MONO_R_MASK (0x1)
777 #define RT5665_M_DAC_L1_STO2_L (0x1 << 15)
779 #define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14)
781 #define RT5665_M_DAC_L2_STO2_L (0x1 << 13)
783 #define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
785 #define RT5665_M_DAC_L3_STO2_L (0x1 << 11)
787 #define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10)
789 #define RT5665_M_ST_DAC_L1 (0x1 << 9)
791 #define RT5665_M_ST_DAC_R1 (0x1 << 8)
793 #define RT5665_M_DAC_R1_STO2_R (0x1 << 7)
795 #define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6)
797 #define RT5665_M_DAC_R2_STO2_R (0x1 << 5)
799 #define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4)
801 #define RT5665_M_DAC_R3_STO2_R (0x1 << 3)
803 #define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2)
817 #define RT5665_A_DACL2_SEL (0x1 << 4)
819 #define RT5665_A_DACR2_SEL (0x1 << 0)
845 #define RT5665_M_PDM1_L (0x1 << 14)
847 #define RT5665_M_PDM1_R (0x1 << 12)
853 #define RT5665_PDM1_BUSY (0x1 << 6)
854 #define RT5665_PDM_PATTERN (0x1 << 5)
855 #define RT5665_PDM_GAIN (0x1 << 4)
856 #define RT5665_LRCK_PDM_PI2C (0x1 << 3)
864 #define RT5665_M_CBJ_RM1_L (0x1 << 7)
866 #define RT5665_M_BST1_RM1_L (0x1 << 5)
868 #define RT5665_M_BST2_RM1_L (0x1 << 4)
870 #define RT5665_M_BST3_RM1_L (0x1 << 3)
872 #define RT5665_M_BST4_RM1_L (0x1 << 2)
874 #define RT5665_M_INL_RM1_L (0x1 << 1)
876 #define RT5665_M_INR_RM1_L (0x1)
880 #define RT5665_M_AEC_REF_RM1_R (0x1 << 7)
882 #define RT5665_M_BST1_RM1_R (0x1 << 5)
884 #define RT5665_M_BST2_RM1_R (0x1 << 4)
886 #define RT5665_M_BST3_RM1_R (0x1 << 3)
888 #define RT5665_M_BST4_RM1_R (0x1 << 2)
890 #define RT5665_M_INR_RM1_R (0x1 << 1)
892 #define RT5665_M_MONOVOL_RM1_R (0x1)
896 #define RT5665_M_CBJ_RM2_L (0x1 << 7)
898 #define RT5665_M_BST1_RM2_L (0x1 << 5)
900 #define RT5665_M_BST2_RM2_L (0x1 << 4)
902 #define RT5665_M_BST3_RM2_L (0x1 << 3)
904 #define RT5665_M_BST4_RM2_L (0x1 << 2)
906 #define RT5665_M_INL_RM2_L (0x1 << 1)
908 #define RT5665_M_INR_RM2_L (0x1)
912 #define RT5665_M_MONOVOL_RM2_R (0x1 << 7)
914 #define RT5665_M_BST1_RM2_R (0x1 << 5)
916 #define RT5665_M_BST2_RM2_R (0x1 << 4)
918 #define RT5665_M_BST3_RM2_R (0x1 << 3)
920 #define RT5665_M_BST4_RM2_R (0x1 << 2)
922 #define RT5665_M_INL_RM2_R (0x1 << 1)
924 #define RT5665_M_INR_RM2_R (0x1)
928 #define RT5665_M_BST3_SM_L (0x1 << 4)
930 #define RT5665_M_IN_R_SM_L (0x1 << 3)
932 #define RT5665_M_IN_L_SM_L (0x1 << 2)
934 #define RT5665_M_BST1_SM_L (0x1 << 1)
936 #define RT5665_M_DAC_L2_SM_L (0x1)
940 #define RT5665_M_BST3_SM_R (0x1 << 4)
942 #define RT5665_M_IN_R_SM_R (0x1 << 3)
944 #define RT5665_M_IN_L_SM_R (0x1 << 2)
946 #define RT5665_M_BST4_SM_R (0x1 << 1)
948 #define RT5665_M_DAC_R2_SM_R (0x1)
952 #define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)
954 #define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
956 #define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)
958 #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
962 #define RT5665_G_MONOVOL_MA (0x1 << 10)
964 #define RT5665_M_MONOVOL_MA (0x1 << 9)
966 #define RT5665_M_DAC_L2_MA (0x1 << 8)
968 #define RT5665_M_BST3_MM (0x1 << 4)
970 #define RT5665_M_BST2_MM (0x1 << 3)
972 #define RT5665_M_BST1_MM (0x1 << 2)
974 #define RT5665_M_RECMIC2L_MM (0x1 << 1)
976 #define RT5665_M_DAC_L2_MM (0x1)
992 #define RT5665_M_BST3_OM_L (0x1 << 4)
994 #define RT5665_M_BST2_OM_L (0x1 << 3)
996 #define RT5665_M_BST1_OM_L (0x1 << 2)
998 #define RT5665_M_IN_L_OM_L (0x1 << 1)
1000 #define RT5665_M_DAC_L2_OM_L (0x1)
1004 #define RT5665_M_BST4_OM_R (0x1 << 4)
1006 #define RT5665_M_BST3_OM_R (0x1 << 3)
1008 #define RT5665_M_BST2_OM_R (0x1 << 2)
1010 #define RT5665_M_IN_R_OM_R (0x1 << 1)
1012 #define RT5665_M_DAC_R2_OM_R (0x1)
1016 #define RT5665_M_DAC_L2_LM (0x1 << 15)
1018 #define RT5665_M_DAC_R2_LM (0x1 << 14)
1020 #define RT5665_M_OV_L_LM (0x1 << 13)
1022 #define RT5665_M_OV_R_LM (0x1 << 12)
1025 #define RT5665_LOUT_DF (0x1 << 11)
1029 #define RT5665_PWR_I2S1_1 (0x1 << 15)
1031 #define RT5665_PWR_I2S1_2 (0x1 << 14)
1033 #define RT5665_PWR_I2S2_1 (0x1 << 13)
1035 #define RT5665_PWR_I2S2_2 (0x1 << 12)
1037 #define RT5665_PWR_DAC_L1 (0x1 << 11)
1039 #define RT5665_PWR_DAC_R1 (0x1 << 10)
1041 #define RT5665_PWR_I2S3 (0x1 << 9)
1043 #define RT5665_PWR_LDO (0x1 << 8)
1045 #define RT5665_PWR_DAC_L2 (0x1 << 7)
1047 #define RT5665_PWR_DAC_R2 (0x1 << 6)
1049 #define RT5665_PWR_ADC_L1 (0x1 << 4)
1051 #define RT5665_PWR_ADC_R1 (0x1 << 3)
1053 #define RT5665_PWR_ADC_L2 (0x1 << 2)
1055 #define RT5665_PWR_ADC_R2 (0x1 << 1)
1059 #define RT5665_PWR_ADC_S1F (0x1 << 15)
1061 #define RT5665_PWR_ADC_S2F (0x1 << 14)
1063 #define RT5665_PWR_ADC_MF_L (0x1 << 13)
1065 #define RT5665_PWR_ADC_MF_R (0x1 << 12)
1067 #define RT5665_PWR_DAC_S2F (0x1 << 11)
1069 #define RT5665_PWR_DAC_S1F (0x1 << 10)
1071 #define RT5665_PWR_DAC_MF_L (0x1 << 9)
1073 #define RT5665_PWR_DAC_MF_R (0x1 << 8)
1075 #define RT5665_PWR_PDM1 (0x1 << 7)
1079 #define RT5665_PWR_VREF1 (0x1 << 15)
1081 #define RT5665_PWR_FV1 (0x1 << 14)
1083 #define RT5665_PWR_VREF2 (0x1 << 13)
1085 #define RT5665_PWR_FV2 (0x1 << 12)
1087 #define RT5665_PWR_VREF3 (0x1 << 11)
1089 #define RT5665_PWR_FV3 (0x1 << 10)
1091 #define RT5665_PWR_MB (0x1 << 9)
1093 #define RT5665_PWR_LM (0x1 << 8)
1095 #define RT5665_PWR_BG (0x1 << 7)
1097 #define RT5665_PWR_MA (0x1 << 6)
1099 #define RT5665_PWR_HA_L (0x1 << 5)
1101 #define RT5665_PWR_HA_R (0x1 << 4)
1105 #define RT5665_HP_DRIVER_3X (0x1 << 2)
1109 #define RT5665_LDO1_DVO_10 (0x1)
1114 #define RT5665_PWR_BST1 (0x1 << 15)
1116 #define RT5665_PWR_BST2 (0x1 << 14)
1118 #define RT5665_PWR_BST3 (0x1 << 13)
1120 #define RT5665_PWR_BST4 (0x1 << 12)
1122 #define RT5665_PWR_MB1 (0x1 << 11)
1125 #define RT5665_PWR_MB2 (0x1 << 10)
1128 #define RT5665_PWR_MB3 (0x1 << 9)
1130 #define RT5665_PWR_BST1_P (0x1 << 7)
1132 #define RT5665_PWR_BST2_P (0x1 << 6)
1134 #define RT5665_PWR_BST3_P (0x1 << 5)
1136 #define RT5665_PWR_BST4_P (0x1 << 4)
1138 #define RT5665_PWR_JD1 (0x1 << 3)
1140 #define RT5665_PWR_JD2 (0x1 << 2)
1142 #define RT5665_PWR_RM1_L (0x1 << 1)
1144 #define RT5665_PWR_RM1_R (0x1)
1148 #define RT5665_PWR_CBJ (0x1 << 9)
1150 #define RT5665_PWR_BST_L (0x1 << 8)
1152 #define RT5665_PWR_BST_R (0x1 << 7)
1154 #define RT5665_PWR_PLL (0x1 << 6)
1156 #define RT5665_PWR_LDO2 (0x1 << 2)
1158 #define RT5665_PWR_SVD (0x1 << 1)
1162 #define RT5665_PWR_RM2_L (0x1 << 15)
1164 #define RT5665_PWR_RM2_R (0x1 << 14)
1166 #define RT5665_PWR_OM_L (0x1 << 13)
1168 #define RT5665_PWR_OM_R (0x1 << 12)
1170 #define RT5665_PWR_MM (0x1 << 11)
1172 #define RT5665_PWR_AEC_REF (0x1 << 6)
1174 #define RT5665_PWR_STO1_DAC_L (0x1 << 5)
1176 #define RT5665_PWR_STO1_DAC_R (0x1 << 4)
1178 #define RT5665_PWR_MONO_DAC_L (0x1 << 3)
1180 #define RT5665_PWR_MONO_DAC_R (0x1 << 2)
1182 #define RT5665_PWR_STO2_DAC_L (0x1 << 1)
1184 #define RT5665_PWR_STO2_DAC_R (0x1)
1188 #define RT5665_PWR_OV_L (0x1 << 13)
1190 #define RT5665_PWR_OV_R (0x1 << 12)
1192 #define RT5665_PWR_IN_L (0x1 << 9)
1194 #define RT5665_PWR_IN_R (0x1 << 8)
1196 #define RT5665_PWR_MV (0x1 << 7)
1198 #define RT5665_PWR_MIC_DET (0x1 << 5)
1209 #define RT5665_DMIC_1_EN_MASK (0x1 << 15)
1212 #define RT5665_DMIC_1_EN (0x1 << 15)
1213 #define RT5665_DMIC_2_EN_MASK (0x1 << 14)
1216 #define RT5665_DMIC_2_EN (0x1 << 14)
1217 #define RT5665_DMIC_2_DP_MASK (0x1 << 9)
1220 #define RT5665_DMIC_2_DP_IN2P (0x1 << 9)
1223 #define RT5665_DMIC_1_DP_MASK (0x1 << 1)
1226 #define RT5665_DMIC_1_DP_IN2N (0x1 << 1)
1230 #define RT5665_DMIC_2L_LH_MASK (0x1 << 3)
1233 #define RT5665_DMIC_2L_LH_FALLING (0x1 << 3)
1234 #define RT5665_DMIC_2R_LH_MASK (0x1 << 2)
1237 #define RT5665_DMIC_2R_LH_FALLING (0x1 << 2)
1238 #define RT5665_DMIC_1L_LH_MASK (0x1 << 1)
1241 #define RT5665_DMIC_1L_LH_FALLING (0x1 << 1)
1242 #define RT5665_DMIC_1R_LH_MASK (0x1 << 0)
1245 #define RT5665_DMIC_1R_LH_FALLING (0x1)
1248 #define RT5665_I2S_MS_MASK (0x1 << 15)
1251 #define RT5665_I2S_MS_S (0x1 << 15)
1252 #define RT5665_I2S_PIN_CFG_MASK (0x1 << 14)
1254 #define RT5665_I2S_CLK_SEL_MASK (0x1 << 11)
1256 #define RT5665_I2S_BP_MASK (0x1 << 8)
1259 #define RT5665_I2S_BP_INV (0x1 << 8)
1263 #define RT5665_I2S_DL_20 (0x1 << 4)
1269 #define RT5665_I2S_DF_LEFT (0x1)
1279 #define RT5665_I2S_PD1_2 (0x1 << 12)
1289 #define RT5665_I2S_M_PD2_2 (0x1 << 8)
1299 #define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4)
1304 #define RT5665_DAC_OSR_64 (0x1 << 2)
1309 #define RT5665_ADC_OSR_64 (0x1)
1313 #define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)
1316 #define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)
1320 #define RT5665_I2S_PD2_2 (0x1 << 12)
1327 #define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11)
1330 #define RT5665_I2S_BCLK_MS3_64 (0x1 << 11)
1334 #define RT5665_I2S_PD3_2 (0x1 << 8)
1344 #define RT5665_I2S_PD4_2 (0x1 << 4)
1353 #define RT5665_I2S1_MODE_MASK (0x1 << 15)
1355 #define RT5665_I2S1_MODE_TDM (0x1 << 15)
1358 #define RT5665_TDM_IN_CH_4 (0x1 << 10)
1363 #define RT5665_TDM_OUT_CH_4 (0x1 << 8)
1368 #define RT5665_TDM_IN_LEN_20 (0x1 << 6)
1373 #define RT5665_TDM_OUT_LEN_20 (0x1 << 4)
1401 #define RT5665_SCLK_SRC_PLL1 (0x1 << 14)
1406 #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
1427 #define RT5665_PLL_M_BP (0x1 << 11)
1429 #define RT5665_PLL_K_BP (0x1 << 10)
1433 #define RT5665_I2S3_ASRC_MASK (0x1 << 15)
1435 #define RT5665_I2S2_ASRC_MASK (0x1 << 14)
1437 #define RT5665_I2S1_ASRC_MASK (0x1 << 13)
1439 #define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
1441 #define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11)
1443 #define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10)
1445 #define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)
1447 #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
1449 #define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7)
1451 #define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6)
1453 #define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5)
1455 #define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4)
1457 #define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3)
1459 #define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2)
1461 #define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1)
1493 #define RT5665_PUMP_EN (0x1 << 3)
1496 #define RT5665_DEPOP_MASK (0x1 << 13)
1499 #define RT5665_DEPOP_MAN (0x1 << 13)
1500 #define RT5665_RAMP_MASK (0x1 << 12)
1503 #define RT5665_RAMP_EN (0x1 << 12)
1504 #define RT5665_BPS_MASK (0x1 << 11)
1507 #define RT5665_BPS_EN (0x1 << 11)
1508 #define RT5665_FAST_UPDN_MASK (0x1 << 10)
1511 #define RT5665_FAST_UPDN_EN (0x1 << 10)
1515 #define RT5665_MRES_25MO (0x1 << 8)
1518 #define RT5665_VLO_MASK (0x1 << 7)
1521 #define RT5665_VLO_32V (0x1 << 7)
1522 #define RT5665_DIG_DP_MASK (0x1 << 6)
1525 #define RT5665_DIG_DP_EN (0x1 << 6)
1548 #define RT5665_OSW_L_MASK (0x1 << 11)
1551 #define RT5665_OSW_L_EN (0x1 << 11)
1552 #define RT5665_OSW_R_MASK (0x1 << 10)
1555 #define RT5665_OSW_R_EN (0x1 << 10)
1559 #define RT5665_PM_HP_MV (0x1 << 8)
1564 #define RT5665_IB_HP_25IL (0x1 << 6)
1569 #define RT5665_PVDD_DET_MASK (0x1 << 15)
1572 #define RT5665_PVDD_DET_EN (0x1 << 15)
1573 #define RT5665_SPK_AG_MASK (0x1 << 14)
1576 #define RT5665_SPK_AG_EN (0x1 << 14)
1579 #define RT5665_MIC1_BS_MASK (0x1 << 15)
1582 #define RT5665_MIC1_BS_75AV (0x1 << 15)
1583 #define RT5665_MIC2_BS_MASK (0x1 << 14)
1586 #define RT5665_MIC2_BS_75AV (0x1 << 14)
1587 #define RT5665_MIC1_CLK_MASK (0x1 << 13)
1590 #define RT5665_MIC1_CLK_EN (0x1 << 13)
1591 #define RT5665_MIC2_CLK_MASK (0x1 << 12)
1594 #define RT5665_MIC2_CLK_EN (0x1 << 12)
1595 #define RT5665_MIC1_OVCD_MASK (0x1 << 11)
1598 #define RT5665_MIC1_OVCD_EN (0x1 << 11)
1602 #define RT5665_MIC1_OVTH_1500UA (0x1 << 9)
1604 #define RT5665_MIC2_OVCD_MASK (0x1 << 8)
1607 #define RT5665_MIC2_OVCD_EN (0x1 << 8)
1611 #define RT5665_MIC2_OVTH_1500UA (0x1 << 6)
1613 #define RT5665_PWR_MB_MASK (0x1 << 5)
1616 #define RT5665_PWR_MB_PU (0x1 << 5)
1619 #define RT5665_PWR_CLK25M_MASK (0x1 << 9)
1622 #define RT5665_PWR_CLK25M_PU (0x1 << 9)
1623 #define RT5665_PWR_CLK1M_MASK (0x1 << 8)
1626 #define RT5665_PWR_CLK1M_PU (0x1 << 8)
1630 #define RT5665_CLK_SRC_PLL1 (0x1)
1633 #define RT5665_I2S_PD_2 (0x1)
1652 #define RT5665_EQ_SRC_ADC (0x1 << 15)
1653 #define RT5665_EQ_UPD (0x1 << 14)
1655 #define RT5665_EQ_CD_MASK (0x1 << 13)
1658 #define RT5665_EQ_CD_EN (0x1 << 13)
1662 #define RT5665_EQ_DITH_LSB (0x1 << 8)
1667 #define RT5665_JD1_1_EN_MASK (0x1 << 15)
1670 #define RT5665_JD1_1_EN (0x1 << 15)
1671 #define RT5665_JD1_2_EN_MASK (0x1 << 12)
1674 #define RT5665_JD1_2_EN (0x1 << 12)
1677 #define RT5665_IL_IRQ_MASK (0x1 << 6)
1679 #define RT5665_IL_IRQ_EN (0x1 << 6)
1682 #define RT5665_IRQ_JD_EN (0x1 << 3)
1686 #define RT5665_GP1_PIN_MASK (0x1 << 15)
1689 #define RT5665_GP1_PIN_IRQ (0x1 << 15)
1693 #define RT5665_GP2_PIN_BCLK2 (0x1 << 13)
1698 #define RT5665_GP3_PIN_LRCK2 (0x1 << 11)
1703 #define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)
1708 #define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7)
1713 #define RT5665_GP6_PIN_BCLK3 (0x1 << 5)
1718 #define RT5665_GP7_PIN_LRCK3 (0x1 << 3)
1723 #define RT5665_GP8_PIN_DACDAT3 (0x1 << 1)
1732 #define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14)
1738 #define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
1740 #define RT5665_GP1_PF_MASK (0x1 << 11)
1742 #define RT5665_GP1_PF_OUT (0x1 << 11)
1743 #define RT5665_GP1_OUT_MASK (0x1 << 10)
1745 #define RT5665_GP1_OUT_L (0x1 << 10)
1746 #define RT5665_GP2_PF_MASK (0x1 << 9)
1748 #define RT5665_GP2_PF_OUT (0x1 << 9)
1749 #define RT5665_GP2_OUT_MASK (0x1 << 8)
1751 #define RT5665_GP2_OUT_L (0x1 << 8)
1752 #define RT5665_GP3_PF_MASK (0x1 << 7)
1754 #define RT5665_GP3_PF_OUT (0x1 << 7)
1755 #define RT5665_GP3_OUT_MASK (0x1 << 6)
1757 #define RT5665_GP3_OUT_L (0x1 << 6)
1758 #define RT5665_GP4_PF_MASK (0x1 << 5)
1760 #define RT5665_GP4_PF_OUT (0x1 << 5)
1761 #define RT5665_GP4_OUT_MASK (0x1 << 4)
1763 #define RT5665_GP4_OUT_L (0x1 << 4)
1764 #define RT5665_GP5_PF_MASK (0x1 << 3)
1766 #define RT5665_GP5_PF_OUT (0x1 << 3)
1767 #define RT5665_GP5_OUT_MASK (0x1 << 2)
1769 #define RT5665_GP5_OUT_L (0x1 << 2)
1770 #define RT5665_GP6_PF_MASK (0x1 << 1)
1772 #define RT5665_GP6_PF_OUT (0x1 << 1)
1773 #define RT5665_GP6_OUT_MASK (0x1)
1775 #define RT5665_GP6_OUT_L (0x1)
1779 #define RT5665_GP7_PF_MASK (0x1 << 15)
1781 #define RT5665_GP7_PF_OUT (0x1 << 15)
1782 #define RT5665_GP7_OUT_MASK (0x1 << 14)
1784 #define RT5665_GP7_OUT_L (0x1 << 14)
1785 #define RT5665_GP8_PF_MASK (0x1 << 13)
1787 #define RT5665_GP8_PF_OUT (0x1 << 13)
1788 #define RT5665_GP8_OUT_MASK (0x1 << 12)
1790 #define RT5665_GP8_OUT_L (0x1 << 12)
1791 #define RT5665_GP9_PF_MASK (0x1 << 11)
1793 #define RT5665_GP9_PF_OUT (0x1 << 11)
1794 #define RT5665_GP9_OUT_MASK (0x1 << 10)
1796 #define RT5665_GP9_OUT_L (0x1 << 10)
1797 #define RT5665_GP10_PF_MASK (0x1 << 9)
1799 #define RT5665_GP10_PF_OUT (0x1 << 9)
1800 #define RT5665_GP10_OUT_MASK (0x1 << 8)
1802 #define RT5665_GP10_OUT_L (0x1 << 8)
1803 #define RT5665_GP11_PF_MASK (0x1 << 7)
1805 #define RT5665_GP11_PF_OUT (0x1 << 7)
1806 #define RT5665_GP11_OUT_MASK (0x1 << 6)
1808 #define RT5665_GP11_OUT_L (0x1 << 6)
1811 #define RT5665_SV_MASK (0x1 << 15)
1814 #define RT5665_SV_EN (0x1 << 15)
1815 #define RT5665_OUT_SV_MASK (0x1 << 13)
1818 #define RT5665_OUT_SV_EN (0x1 << 13)
1819 #define RT5665_HP_SV_MASK (0x1 << 12)
1822 #define RT5665_HP_SV_EN (0x1 << 12)
1823 #define RT5665_ZCD_DIG_MASK (0x1 << 11)
1826 #define RT5665_ZCD_DIG_EN (0x1 << 11)
1827 #define RT5665_ZCD_MASK (0x1 << 10)
1830 #define RT5665_ZCD_PU (0x1 << 10)
1835 #define RT5665_ZCD_HP_MASK (0x1 << 15)
1838 #define RT5665_ZCD_HP_EN (0x1 << 15)
1841 #define RT5665_4BTN_IL_MASK (0x1 << 15)
1842 #define RT5665_4BTN_IL_EN (0x1 << 15)
1844 #define RT5665_4BTN_IL_RST_MASK (0x1 << 14)
1845 #define RT5665_4BTN_IL_NOR (0x1 << 14)
1851 #define RT5665_JD1_MODE_1 (0x1 << 0)
1858 #define RT5665_JD_HPO_JD1_1 (0x1)
1866 #define RT5665_AM_MASK (0x1 << 7)
1867 #define RT5665_AM_EN (0x1 << 7)
1868 #define RT5665_AM_DIS (0x1 << 7)
1869 #define RT5665_DIG_GATE_CTRL 0x1
1873 #define RT5665_M_RF_DIG_MASK (0x1 << 12)
1875 #define RT5665_M_RI_DIG (0x1 << 11)
1878 #define RT5665_CKXEN_DAC1_MASK (0x1 << 13)
1880 #define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
1882 #define RT5665_CKXEN_DAC2_MASK (0x1 << 5)
1884 #define RT5665_CKGEN_DAC2_MASK (0x1 << 4)
1888 #define RT5665_CKXEN_ADC1_MASK (0x1 << 13)
1890 #define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
1892 #define RT5665_CKXEN_ADC2_MASK (0x1 << 5)
1894 #define RT5665_CKGEN_ADC2_MASK (0x1 << 4)
1898 #define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)
1899 #define RT5665_SEL_CLK_VOL_EN (0x1 << 15)
1903 #define RT5665_AD2DA_LB_MASK (0x1 << 9)
1907 #define RT5665_NG2_EN_MASK (0x1 << 15)
1908 #define RT5665_NG2_EN (0x1 << 15)
1916 #define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)
1917 #define RT5665_SAR_BUTT_DET_EN (0x1 << 15)
1919 #define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14)
1920 #define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14)
1922 #define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)
1923 #define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1925 #define RT5665_SAR_POW_MASK (0x1 << 12)
1926 #define RT5665_SAR_POW_EN (0x1 << 12)
1928 #define RT5665_SAR_RST_MASK (0x1 << 11)
1929 #define RT5665_SAR_RST_NORMAL (0x1 << 11)
1931 #define RT5665_SAR_BYPASS_MASK (0x1 << 10)
1932 #define RT5665_SAR_BYPASS_EN (0x1 << 10)
1934 #define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)
1935 #define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)
1937 #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
1938 #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
1940 #define RT5665_SAR_SEL_MODE_MASK (0x1 << 7)
1941 #define RT5665_SAR_SEL_MODE_CMP (0x1 << 7)
1943 #define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
1944 #define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
1946 #define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1947 #define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1982 RT5665_DA_STEREO1_FILTER = 0x1,
1983 RT5665_DA_STEREO2_FILTER = (0x1 << 1),
1984 RT5665_DA_MONO_L_FILTER = (0x1 << 2),
1985 RT5665_DA_MONO_R_FILTER = (0x1 << 3),
1986 RT5665_AD_STEREO1_FILTER = (0x1 << 4),
1987 RT5665_AD_STEREO2_FILTER = (0x1 << 5),
1988 RT5665_AD_MONO_L_FILTER = (0x1 << 6),
1989 RT5665_AD_MONO_R_FILTER = (0x1 << 7),