Lines Matching full:x1
176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 << 7)
214 #define RT5651_INR_SEL_MONON (0x1 << 7)
231 #define RT5651_M_DAC_L2_VOL (0x1 << 13)
233 #define RT5651_M_DAC_R2_VOL (0x1 << 12)
235 #define RT5651_SEL_DAC_L2 (0x1 << 11)
236 #define RT5651_IF2_DAC_L2 (0x1 << 11)
239 #define RT5651_SEL_DAC_R2 (0x1 << 10)
240 #define RT5651_IF2_DAC_R2 (0x1 << 11)
251 #define RT5651_M_MONO_ADC_L (0x1 << 15)
255 #define RT5651_M_MONO_ADC_R (0x1 << 7)
269 #define RT5651_M_STO1_ADC_L1 (0x1 << 14)
271 #define RT5651_M_STO1_ADC_L2 (0x1 << 13)
273 #define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
275 #define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
277 #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
280 #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
281 #define RT5651_M_STO1_ADC_R1 (0x1 << 6)
283 #define RT5651_M_STO1_ADC_R2 (0x1 << 5)
287 #define RT5651_M_STO2_ADC_L1 (0x1 << 14)
289 #define RT5651_M_STO2_ADC_L2 (0x1 << 13)
291 #define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
294 #define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
295 #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
298 #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
299 #define RT5651_M_STO2_ADC_R1 (0x1 << 6)
301 #define RT5651_M_STO2_ADC_R2 (0x1 << 5)
303 #define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
305 #define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
307 #define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
310 #define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
313 #define RT5651_M_ADCMIX_L (0x1 << 15)
315 #define RT5651_M_IF1_DAC_L (0x1 << 14)
317 #define RT5651_M_ADCMIX_R (0x1 << 7)
319 #define RT5651_M_IF1_DAC_R (0x1 << 6)
323 #define RT5651_M_DAC_L1_MIXL (0x1 << 14)
325 #define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
327 #define RT5651_M_DAC_L2_MIXL (0x1 << 12)
329 #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
331 #define RT5651_M_DAC_R1_MIXL (0x1 << 9)
333 #define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
335 #define RT5651_M_DAC_R1_MIXR (0x1 << 6)
337 #define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
339 #define RT5651_M_DAC_R2_MIXR (0x1 << 4)
341 #define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
343 #define RT5651_M_DAC_L1_MIXR (0x1 << 1)
345 #define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
349 #define RT5651_M_STO_DD_L1 (0x1 << 14)
351 #define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
353 #define RT5651_M_STO_DD_L2 (0x1 << 12)
355 #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
357 #define RT5651_M_STO_DD_R2_L (0x1 << 10)
359 #define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
361 #define RT5651_M_STO_DD_R1 (0x1 << 6)
363 #define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
365 #define RT5651_M_STO_DD_R2 (0x1 << 4)
367 #define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
369 #define RT5651_M_STO_DD_L2_R (0x1 << 2)
371 #define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
375 #define RT5651_M_STO_L_DAC_L (0x1 << 15)
377 #define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
379 #define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
381 #define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
383 #define RT5651_M_STO_R_DAC_R (0x1 << 11)
385 #define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
387 #define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
389 #define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
393 #define RT5651_RXDP_SRC_MASK (0x1 << 15)
396 #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
397 #define RT5651_TXDP_SRC_MASK (0x1 << 14)
400 #define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
406 #define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
412 #define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
414 #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
417 #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
418 #define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
421 #define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
425 #define RT5651_RXDC_SEL_L2R (0x1 << 8)
431 #define RT5651_RXDP_SEL_L2R (0x1 << 6)
437 #define RT5651_TXDC_SEL_L2R (0x1 << 4)
443 #define RT5651_TXDP_SEL_L2R (0x1 << 2)
451 #define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
457 #define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
460 #define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
463 #define RT5651_IF1_ADC2 (0x1 << 7)
466 #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
469 #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
470 #define RT5651_M_PDM_L (0x1 << 14)
472 #define RT5651_PDM_R_SEL_MASK (0x1 << 13)
475 #define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
476 #define RT5651_M_PDM_R (0x1 << 12)
478 #define RT5651_PDM_BUSY (0x1 << 6)
480 #define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
482 #define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
483 #define RT5651_PDM_VOL_MASK (0x1 << 4)
494 #define PT5631_PDM_CMD_EXE (0x1 << 11)
495 #define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
497 #define RT5651_PDM_I2C_CMD_W (0x1 << 10)
498 #define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
500 #define RT5651_PDM_I2C_BUSY (0x1 << 8)
522 #define RT5651_M_IN2_L_RM_L (0x1 << 6)
524 #define RT5651_M_IN1_L_RM_L (0x1 << 5)
526 #define RT5651_M_BST3_RM_L (0x1 << 3)
528 #define RT5651_M_BST2_RM_L (0x1 << 2)
530 #define RT5651_M_BST1_RM_L (0x1 << 1)
532 #define RT5651_M_OM_L_RM_L (0x1)
550 #define RT5651_M_IN2_R_RM_R (0x1 << 6)
552 #define RT5651_M_IN1_R_RM_R (0x1 << 5)
554 #define RT5651_M_BST3_RM_R (0x1 << 3)
556 #define RT5651_M_BST2_RM_R (0x1 << 2)
558 #define RT5651_M_BST1_RM_R (0x1 << 1)
560 #define RT5651_M_OM_R_RM_R (0x1)
564 #define RT5651_M_DAC1_HM (0x1 << 14)
566 #define RT5651_M_HPVOL_HM (0x1 << 13)
568 #define RT5651_G_HPOMIX_MASK (0x1 << 12)
582 #define RT5651_M_RM_L_SM_L (0x1 << 5)
584 #define RT5651_M_IN_L_SM_L (0x1 << 4)
586 #define RT5651_M_DAC_L1_SM_L (0x1 << 3)
588 #define RT5651_M_DAC_L2_SM_L (0x1 << 2)
590 #define RT5651_M_OM_L_SM_L (0x1 << 1)
604 #define RT5651_M_RM_R_SM_R (0x1 << 5)
606 #define RT5651_M_IN_R_SM_R (0x1 << 4)
608 #define RT5651_M_DAC_R1_SM_R (0x1 << 3)
610 #define RT5651_M_DAC_R2_SM_R (0x1 << 2)
612 #define RT5651_M_OM_R_SM_R (0x1 << 1)
616 #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
618 #define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
620 #define RT5651_M_SV_R_SPM_L (0x1 << 13)
622 #define RT5651_M_SV_L_SPM_L (0x1 << 12)
624 #define RT5651_M_BST1_SPM_L (0x1 << 11)
628 #define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
630 #define RT5651_M_SV_R_SPM_R (0x1 << 12)
632 #define RT5651_M_BST1_SPM_R (0x1 << 11)
640 #define RT5651_M_DAC_R2_MM (0x1 << 15)
642 #define RT5651_M_DAC_L2_MM (0x1 << 14)
644 #define RT5651_M_OV_R_MM (0x1 << 13)
646 #define RT5651_M_OV_L_MM (0x1 << 12)
648 #define RT5651_M_BST1_MM (0x1 << 11)
650 #define RT5651_G_MONOMIX_MASK (0x1 << 10)
670 #define RT5651_M_IN2_L_OM_L (0x1 << 9)
672 #define RT5651_M_BST2_OM_L (0x1 << 6)
674 #define RT5651_M_BST1_OM_L (0x1 << 5)
676 #define RT5651_M_IN1_L_OM_L (0x1 << 4)
678 #define RT5651_M_RM_L_OM_L (0x1 << 3)
680 #define RT5651_M_DAC_L1_OM_L (0x1)
700 #define RT5651_M_IN2_R_OM_R (0x1 << 9)
702 #define RT5651_M_BST2_OM_R (0x1 << 6)
704 #define RT5651_M_BST1_OM_R (0x1 << 5)
706 #define RT5651_M_IN1_R_OM_R (0x1 << 4)
708 #define RT5651_M_RM_R_OM_R (0x1 << 3)
710 #define RT5651_M_DAC_R1_OM_R (0x1)
714 #define RT5651_M_DAC_L1_LM (0x1 << 15)
716 #define RT5651_M_DAC_R1_LM (0x1 << 14)
718 #define RT5651_M_OV_L_LM (0x1 << 13)
720 #define RT5651_M_OV_R_LM (0x1 << 12)
722 #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
726 #define RT5651_PWR_I2S1 (0x1 << 15)
728 #define RT5651_PWR_I2S2 (0x1 << 14)
730 #define RT5651_PWR_DAC_L1 (0x1 << 12)
732 #define RT5651_PWR_DAC_R1 (0x1 << 11)
734 #define RT5651_PWR_ADC_L (0x1 << 2)
736 #define RT5651_PWR_ADC_R (0x1 << 1)
740 #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
742 #define RT5651_PWR_ADC_STO2_F (0x1 << 14)
744 #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
746 #define RT5651_PWR_DAC_STO2_F (0x1 << 10)
748 #define RT5651_PWR_PDM (0x1 << 9)
752 #define RT5651_PWR_VREF1 (0x1 << 15)
754 #define RT5651_PWR_FV1 (0x1 << 14)
756 #define RT5651_PWR_MB (0x1 << 13)
758 #define RT5651_PWR_LM (0x1 << 12)
760 #define RT5651_PWR_BG (0x1 << 11)
762 #define RT5651_PWR_HP_L (0x1 << 7)
764 #define RT5651_PWR_HP_R (0x1 << 6)
766 #define RT5651_PWR_HA (0x1 << 5)
768 #define RT5651_PWR_VREF2 (0x1 << 4)
770 #define RT5651_PWR_FV2 (0x1 << 3)
772 #define RT5651_PWR_LDO (0x1 << 2)
781 #define RT5651_PWR_BST1 (0x1 << 15)
783 #define RT5651_PWR_BST2 (0x1 << 14)
785 #define RT5651_PWR_BST3 (0x1 << 13)
787 #define RT5651_PWR_MB1 (0x1 << 11)
789 #define RT5651_PWR_PLL (0x1 << 9)
791 #define RT5651_PWR_BST1_OP2 (0x1 << 5)
793 #define RT5651_PWR_BST2_OP2 (0x1 << 4)
795 #define RT5651_PWR_BST3_OP2 (0x1 << 3)
797 #define RT5651_PWR_JD_M (0x1 << 2)
799 #define RT5651_PWR_JD2 (0x1 << 1)
801 #define RT5651_PWR_JD3 (0x1)
805 #define RT5651_PWR_OM_L (0x1 << 15)
807 #define RT5651_PWR_OM_R (0x1 << 14)
809 #define RT5651_PWR_RM_L (0x1 << 11)
811 #define RT5651_PWR_RM_R (0x1 << 10)
815 #define RT5651_PWR_OV_L (0x1 << 13)
817 #define RT5651_PWR_OV_R (0x1 << 12)
819 #define RT5651_PWR_HV_L (0x1 << 11)
821 #define RT5651_PWR_HV_R (0x1 << 10)
823 #define RT5651_PWR_IN1_L (0x1 << 9)
825 #define RT5651_PWR_IN1_R (0x1 << 8)
827 #define RT5651_PWR_IN2_L (0x1 << 7)
829 #define RT5651_PWR_IN2_R (0x1 << 6)
833 #define RT5651_I2S_MS_MASK (0x1 << 15)
836 #define RT5651_I2S_MS_S (0x1 << 15)
840 #define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
845 #define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
847 #define RT5651_I2S_BP_MASK (0x1 << 7)
850 #define RT5651_I2S_BP_INV (0x1 << 7)
854 #define RT5651_I2S_DL_20 (0x1 << 2)
860 #define RT5651_I2S_DF_LEFT (0x1)
868 #define RT5651_I2S_PD1_2 (0x1 << 12)
875 #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
878 #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
882 #define RT5651_I2S_PD2_2 (0x1 << 8)
892 #define RT5651_DAC_OSR_64 (0x1 << 2)
898 #define RT5651_ADC_OSR_64 (0x1)
903 #define RT5651_DAHPF_EN (0x1 << 11)
905 #define RT5651_ADHPF_EN (0x1 << 10)
909 #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
912 #define RT5651_DMIC_1_EN (0x1 << 15)
913 #define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
916 #define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
917 #define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
920 #define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
924 #define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
930 #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
933 #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
934 #define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
937 #define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
941 #define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
947 #define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
950 #define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
953 #define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
954 #define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
957 #define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
961 #define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
967 #define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
973 #define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
979 #define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
984 #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
987 #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
988 #define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
991 #define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
992 #define RT5651_TDM_CH_VAL_EN (0x1 << 13)
994 #define RT5651_TDM_LPBK_EN (0x1 << 12)
996 #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
999 #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1000 #define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1003 #define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1004 #define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1006 #define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1009 #define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1010 #define RT5651_M_TDM2_L (0x1 << 7)
1012 #define RT5651_M_TDM2_R (0x1 << 6)
1014 #define RT5651_M_TDM4_L (0x1 << 5)
1016 #define RT5651_M_TDM4_R (0x1 << 4)
1023 #define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1033 #define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1043 #define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1053 #define RT5651_CH4_R_SEL_SL1 (0x1)
1065 #define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1070 #define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1072 #define RT5651_PLL1_PD_MASK (0x1 << 3)
1075 #define RT5651_PLL1_PD_2 (0x1 << 3)
1091 #define RT5651_PLL_M_BP (0x1 << 11)
1095 #define RT5651_STO1_T_MASK (0x1 << 15)
1098 #define RT5651_STO1_T_LRCK1 (0x1 << 15)
1099 #define RT5651_STO2_T_MASK (0x1 << 12)
1102 #define RT5651_STO2_T_LRCK2 (0x1 << 12)
1103 #define RT5651_ASRC2_REF_MASK (0x1 << 11)
1106 #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1107 #define RT5651_DMIC_1_M_MASK (0x1 << 9)
1110 #define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1113 #define RT5651_STO1_ASRC_EN (0x1 << 15)
1115 #define RT5651_STO2_ASRC_EN (0x1 << 14)
1117 #define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1120 #define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1121 #define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1124 #define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1125 #define RT5651_ADC_M_MASK (0x1 << 11)
1128 #define RT5651_ADC_M_ASRC (0x1 << 11)
1129 #define RT5651_I2S1_R_D_MASK (0x1 << 4)
1132 #define RT5651_I2S1_R_D_EN (0x1 << 4)
1133 #define RT5651_I2S2_R_D_MASK (0x1 << 3)
1136 #define RT5651_I2S2_R_D_EN (0x1 << 3)
1140 #define RT5651_PRE_SCLK_1024 (0x1)
1148 #define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1150 #define RT5651_ASRC_LP_F_M (0x1 << 2)
1153 #define RT5651_ASRC_LP_F_SB (0x1 << 2)
1157 #define RT5651_FTK_PH_DET_DIV2 (0x1)
1174 #define RT5651_HP_OVCD_MASK (0x1 << 10)
1177 #define RT5651_HP_OVCD_EN (0x1 << 10)
1181 #define RT5651_HP_OC_TH_105 (0x1 << 8)
1186 #define RT5651_SMT_TRIG_MASK (0x1 << 15)
1189 #define RT5651_SMT_TRIG_EN (0x1 << 15)
1190 #define RT5651_HP_L_SMT_MASK (0x1 << 9)
1193 #define RT5651_HP_L_SMT_EN (0x1 << 9)
1194 #define RT5651_HP_R_SMT_MASK (0x1 << 8)
1197 #define RT5651_HP_R_SMT_EN (0x1 << 8)
1198 #define RT5651_HP_CD_PD_MASK (0x1 << 7)
1201 #define RT5651_HP_CD_PD_EN (0x1 << 7)
1202 #define RT5651_RSTN_MASK (0x1 << 6)
1205 #define RT5651_RSTN_EN (0x1 << 6)
1206 #define RT5651_RSTP_MASK (0x1 << 5)
1209 #define RT5651_RSTP_EN (0x1 << 5)
1210 #define RT5651_HP_CO_MASK (0x1 << 4)
1213 #define RT5651_HP_CO_EN (0x1 << 4)
1214 #define RT5651_HP_CP_MASK (0x1 << 3)
1217 #define RT5651_HP_CP_PU (0x1 << 3)
1218 #define RT5651_HP_SG_MASK (0x1 << 2)
1221 #define RT5651_HP_SG_EN (0x1 << 2)
1222 #define RT5651_HP_DP_MASK (0x1 << 1)
1225 #define RT5651_HP_DP_PU (0x1 << 1)
1226 #define RT5651_HP_CB_MASK (0x1)
1229 #define RT5651_HP_CB_PU (0x1)
1232 #define RT5651_DEPOP_MASK (0x1 << 13)
1235 #define RT5651_DEPOP_MAN (0x1 << 13)
1236 #define RT5651_RAMP_MASK (0x1 << 12)
1239 #define RT5651_RAMP_EN (0x1 << 12)
1240 #define RT5651_BPS_MASK (0x1 << 11)
1243 #define RT5651_BPS_EN (0x1 << 11)
1244 #define RT5651_FAST_UPDN_MASK (0x1 << 10)
1247 #define RT5651_FAST_UPDN_EN (0x1 << 10)
1251 #define RT5651_MRES_25MO (0x1 << 8)
1254 #define RT5651_VLO_MASK (0x1 << 7)
1257 #define RT5651_VLO_32V (0x1 << 7)
1258 #define RT5651_DIG_DP_MASK (0x1 << 6)
1261 #define RT5651_DIG_DP_EN (0x1 << 6)
1284 #define RT5651_OSW_L_MASK (0x1 << 11)
1287 #define RT5651_OSW_L_EN (0x1 << 11)
1288 #define RT5651_OSW_R_MASK (0x1 << 10)
1291 #define RT5651_OSW_R_EN (0x1 << 10)
1295 #define RT5651_PM_HP_MV (0x1 << 8)
1300 #define RT5651_IB_HP_25IL (0x1 << 6)
1305 #define RT5651_MIC1_BS_MASK (0x1 << 15)
1308 #define RT5651_MIC1_BS_75AV (0x1 << 15)
1309 #define RT5651_MIC1_CLK_MASK (0x1 << 13)
1312 #define RT5651_MIC1_CLK_EN (0x1 << 13)
1313 #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1316 #define RT5651_MIC1_OVCD_EN (0x1 << 11)
1320 #define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1322 #define RT5651_PWR_MB_MASK (0x1 << 5)
1325 #define RT5651_PWR_MB_PU (0x1 << 5)
1326 #define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1329 #define RT5651_PWR_CLK12M_PU (0x1 << 4)
1334 #define RT5651_JD_PU (0x1 << 11)
1336 #define RT5651_JD_PD (0x1 << 10)
1341 #define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1345 #define RT5651_JD_M_PU (0x1 << 3)
1347 #define RT5651_JD_M_PD (0x1 << 2)
1352 #define RT5651_JD_M_MODE_SEL_M1 (0x1)
1360 #define RT5651_EQ_SRC_MASK (0x1 << 15)
1363 #define RT5651_EQ_SRC_ADC (0x1 << 15)
1364 #define RT5651_EQ_UPD (0x1 << 14)
1366 #define RT5651_EQ_CD_MASK (0x1 << 13)
1369 #define RT5651_EQ_CD_EN (0x1 << 13)
1373 #define RT5651_EQ_DITH_LSB (0x1 << 8)
1376 #define RT5651_EQ_CD_F (0x1 << 7)
1378 #define RT5651_EQ_STA_HP2 (0x1 << 6)
1380 #define RT5651_EQ_STA_HP1 (0x1 << 5)
1382 #define RT5651_EQ_STA_BP4 (0x1 << 4)
1384 #define RT5651_EQ_STA_BP3 (0x1 << 3)
1386 #define RT5651_EQ_STA_BP2 (0x1 << 2)
1388 #define RT5651_EQ_STA_BP1 (0x1 << 1)
1390 #define RT5651_EQ_STA_LP (0x1)
1394 #define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1397 #define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1398 #define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1401 #define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1402 #define RT5651_EQ_HPF2_MASK (0x1 << 6)
1405 #define RT5651_EQ_HPF2_EN (0x1 << 6)
1406 #define RT5651_EQ_HPF1_MASK (0x1 << 5)
1409 #define RT5651_EQ_HPF1_EN (0x1 << 5)
1410 #define RT5651_EQ_BPF4_MASK (0x1 << 4)
1413 #define RT5651_EQ_BPF4_EN (0x1 << 4)
1414 #define RT5651_EQ_BPF3_MASK (0x1 << 3)
1417 #define RT5651_EQ_BPF3_EN (0x1 << 3)
1418 #define RT5651_EQ_BPF2_MASK (0x1 << 2)
1421 #define RT5651_EQ_BPF2_EN (0x1 << 2)
1422 #define RT5651_EQ_BPF1_MASK (0x1 << 1)
1425 #define RT5651_EQ_BPF1_EN (0x1 << 1)
1426 #define RT5651_EQ_LPF_MASK (0x1)
1429 #define RT5651_EQ_LPF_EN (0x1)
1433 #define RT5651_MT_MASK (0x1 << 15)
1436 #define RT5651_MT_EN (0x1 << 15)
1439 #define RT5651_ALC_P_MASK (0x1 << 15)
1442 #define RT5651_ALC_P_ADC (0x1 << 15)
1443 #define RT5651_ALC_MASK (0x1 << 14)
1446 #define RT5651_ALC_EN (0x1 << 14)
1447 #define RT5651_ALC_UPD (0x1 << 13)
1453 #define RT5651_ALC_R_48K (0x1 << 5)
1465 #define RT5651_ALC_DRC_MASK (0x1 << 7)
1468 #define RT5651_ALC_DRC_EN (0x1 << 7)
1472 #define RT5651_ALC_CPR_1_2 (0x1 << 5)
1483 #define RT5651_ALC_NG_MASK (0x1 << 6)
1486 #define RT5651_ALC_NG_EN (0x1 << 6)
1487 #define RT5651_ALC_NGH_MASK (0x1 << 5)
1490 #define RT5651_ALC_NGH_EN (0x1 << 5)
1498 #define RT5651_JD_GPIO1 (0x1 << 13)
1504 #define RT5651_JD_HP_MASK (0x1 << 11)
1507 #define RT5651_JD_HP_EN (0x1 << 11)
1508 #define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1511 #define RT5651_JD_HP_TRG_HI (0x1 << 10)
1512 #define RT5651_JD_SPL_MASK (0x1 << 9)
1515 #define RT5651_JD_SPL_EN (0x1 << 9)
1516 #define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1519 #define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1520 #define RT5651_JD_SPR_MASK (0x1 << 7)
1523 #define RT5651_JD_SPR_EN (0x1 << 7)
1524 #define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1527 #define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1528 #define RT5651_JD_LO_MASK (0x1 << 3)
1531 #define RT5651_JD_LO_EN (0x1 << 3)
1532 #define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1535 #define RT5651_JD_LO_TRG_HI (0x1 << 2)
1541 #define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1545 #define RT5651_JD3_IRQ_EN (0x1 << 8)
1547 #define RT5651_JD3_EN_STKY (0x1 << 7)
1549 #define RT5651_JD3_INV (0x1 << 6)
1553 #define RT5651_IRQ_JD_MASK (0x1 << 15)
1556 #define RT5651_IRQ_JD_NOR (0x1 << 15)
1557 #define RT5651_JD_STKY_MASK (0x1 << 13)
1560 #define RT5651_JD_STKY_EN (0x1 << 13)
1561 #define RT5651_JD_P_MASK (0x1 << 11)
1564 #define RT5651_JD_P_INV (0x1 << 11)
1565 #define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1567 #define RT5651_JD1_1_EN_STKY (0x1 << 8)
1569 #define RT5651_JD1_1_INV (0x1 << 7)
1571 #define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1573 #define RT5651_JD1_2_EN_STKY (0x1 << 5)
1575 #define RT5651_JD1_2_INV (0x1 << 4)
1577 #define RT5651_JD2_IRQ_EN (0x1 << 3)
1579 #define RT5651_JD2_EN_STKY (0x1 << 2)
1581 #define RT5651_JD2_INV (0x1 << 1)
1585 #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1588 #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1589 #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1592 #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1593 #define RT5651_MB1_OC_P_MASK (0x1 << 7)
1596 #define RT5651_MB1_OC_P_INV (0x1 << 7)
1597 #define RT5651_MB2_OC_P_MASK (0x1 << 6)
1598 #define RT5651_MB1_OC_CLR (0x1 << 3)
1600 #define RT5651_STA_GPIO8 (0x1)
1604 #define RT5651_STA_JD3 (0x1 << 15)
1606 #define RT5651_STA_JD2 (0x1 << 14)
1608 #define RT5651_STA_JD1_2 (0x1 << 13)
1610 #define RT5651_STA_JD1_1 (0x1 << 12)
1612 #define RT5651_STA_GP7 (0x1 << 11)
1614 #define RT5651_STA_GP6 (0x1 << 10)
1616 #define RT5651_STA_GP5 (0x1 << 9)
1618 #define RT5651_STA_GP1 (0x1 << 8)
1620 #define RT5651_STA_GP2 (0x1 << 7)
1622 #define RT5651_STA_GP3 (0x1 << 6)
1624 #define RT5651_STA_GP4 (0x1 << 5)
1626 #define RT5651_STA_GP_JD (0x1 << 4)
1630 #define RT5651_GP1_PIN_MASK (0x1 << 15)
1633 #define RT5651_GP1_PIN_IRQ (0x1 << 15)
1634 #define RT5651_GP2_PIN_MASK (0x1 << 14)
1637 #define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1638 #define RT5651_GPIO_M_MASK (0x1 << 9)
1641 #define RT5651_GPIO_M_PH (0x1 << 9)
1642 #define RT5651_I2S2_SEL_MASK (0x1 << 8)
1645 #define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1646 #define RT5651_GP5_PIN_MASK (0x1 << 7)
1649 #define RT5651_GP5_PIN_IRQ (0x1 << 7)
1650 #define RT5651_GP6_PIN_MASK (0x1 << 6)
1653 #define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1654 #define RT5651_GP7_PIN_MASK (0x1 << 5)
1657 #define RT5651_GP7_PIN_IRQ (0x1 << 5)
1658 #define RT5651_GP8_PIN_MASK (0x1 << 4)
1661 #define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1662 #define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1665 #define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1668 #define RT5651_GP5_DR_MASK (0x1 << 14)
1671 #define RT5651_GP5_DR_OUT (0x1 << 14)
1672 #define RT5651_GP5_OUT_MASK (0x1 << 13)
1675 #define RT5651_GP5_OUT_HI (0x1 << 13)
1676 #define RT5651_GP5_P_MASK (0x1 << 12)
1679 #define RT5651_GP5_P_INV (0x1 << 12)
1680 #define RT5651_GP4_DR_MASK (0x1 << 11)
1683 #define RT5651_GP4_DR_OUT (0x1 << 11)
1684 #define RT5651_GP4_OUT_MASK (0x1 << 10)
1687 #define RT5651_GP4_OUT_HI (0x1 << 10)
1688 #define RT5651_GP4_P_MASK (0x1 << 9)
1691 #define RT5651_GP4_P_INV (0x1 << 9)
1692 #define RT5651_GP3_DR_MASK (0x1 << 8)
1695 #define RT5651_GP3_DR_OUT (0x1 << 8)
1696 #define RT5651_GP3_OUT_MASK (0x1 << 7)
1699 #define RT5651_GP3_OUT_HI (0x1 << 7)
1700 #define RT5651_GP3_P_MASK (0x1 << 6)
1703 #define RT5651_GP3_P_INV (0x1 << 6)
1704 #define RT5651_GP2_DR_MASK (0x1 << 5)
1707 #define RT5651_GP2_DR_OUT (0x1 << 5)
1708 #define RT5651_GP2_OUT_MASK (0x1 << 4)
1711 #define RT5651_GP2_OUT_HI (0x1 << 4)
1712 #define RT5651_GP2_P_MASK (0x1 << 3)
1715 #define RT5651_GP2_P_INV (0x1 << 3)
1716 #define RT5651_GP1_DR_MASK (0x1 << 2)
1719 #define RT5651_GP1_DR_OUT (0x1 << 2)
1720 #define RT5651_GP1_OUT_MASK (0x1 << 1)
1723 #define RT5651_GP1_OUT_HI (0x1 << 1)
1724 #define RT5651_GP1_P_MASK (0x1)
1727 #define RT5651_GP1_P_INV (0x1)
1730 #define RT5651_GP8_DR_MASK (0x1 << 8)
1733 #define RT5651_GP8_DR_OUT (0x1 << 8)
1734 #define RT5651_GP8_OUT_MASK (0x1 << 7)
1737 #define RT5651_GP8_OUT_HI (0x1 << 7)
1738 #define RT5651_GP8_P_MASK (0x1 << 6)
1741 #define RT5651_GP8_P_INV (0x1 << 6)
1742 #define RT5651_GP7_DR_MASK (0x1 << 5)
1745 #define RT5651_GP7_DR_OUT (0x1 << 5)
1746 #define RT5651_GP7_OUT_MASK (0x1 << 4)
1749 #define RT5651_GP7_OUT_HI (0x1 << 4)
1750 #define RT5651_GP7_P_MASK (0x1 << 3)
1753 #define RT5651_GP7_P_INV (0x1 << 3)
1754 #define RT5651_GP6_DR_MASK (0x1 << 2)
1757 #define RT5651_GP6_DR_OUT (0x1 << 2)
1758 #define RT5651_GP6_OUT_MASK (0x1 << 1)
1761 #define RT5651_GP6_OUT_HI (0x1 << 1)
1762 #define RT5651_GP6_P_MASK (0x1)
1765 #define RT5651_GP6_P_INV (0x1)
1768 #define RT5651_SCB_SWAP_MASK (0x1 << 15)
1771 #define RT5651_SCB_SWAP_EN (0x1 << 15)
1772 #define RT5651_SCB_MASK (0x1 << 14)
1775 #define RT5651_SCB_EN (0x1 << 14)
1778 #define RT5651_BB_MASK (0x1 << 15)
1781 #define RT5651_BB_EN (0x1 << 15)
1785 #define RT5651_BB_CT_B (0x1 << 12)
1788 #define RT5651_M_BB_L_MASK (0x1 << 9)
1790 #define RT5651_M_BB_R_MASK (0x1 << 8)
1792 #define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1794 #define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1800 #define RT5651_M_MP3_L_MASK (0x1 << 15)
1802 #define RT5651_M_MP3_R_MASK (0x1 << 14)
1804 #define RT5651_M_MP3_MASK (0x1 << 13)
1807 #define RT5651_M_MP3_EN (0x1 << 13)
1810 #define RT5651_MP3_HLP_MASK (0x1 << 7)
1813 #define RT5651_MP3_HLP_EN (0x1 << 7)
1814 #define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1816 #define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1820 #define RT5651_MP3_WT_MASK (0x1 << 13)
1823 #define RT5651_MP3_WT_1_2 (0x1 << 13)
1830 #define RT5651_3D_CF_MASK (0x1 << 15)
1833 #define RT5651_3D_CF_EN (0x1 << 15)
1834 #define RT5651_3D_HP_MASK (0x1 << 14)
1837 #define RT5651_3D_HP_EN (0x1 << 14)
1838 #define RT5651_3D_BT_MASK (0x1 << 13)
1841 #define RT5651_3D_BT_EN (0x1 << 13)
1844 #define RT5651_3D_HP_M_MASK (0x1 << 10)
1847 #define RT5651_3D_HP_M_FRO (0x1 << 10)
1848 #define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1850 #define RT5651_M_3D_D2H_MASK (0x1 << 8)
1852 #define RT5651_M_3D_D2R_MASK (0x1 << 7)
1854 #define RT5651_M_3D_REVB_MASK (0x1 << 6)
1858 #define RT5651_2ND_HPF_MASK (0x1 << 15)
1861 #define RT5651_2ND_HPF_EN (0x1 << 15)
1871 #define RT5651_ZD_F_ZC_IM (0x1 << 4)
1882 #define RT5651_SI_DAC_MASK (0x1 << 11)
1885 #define RT5651_SI_DAC_TEST (0x1 << 11)
1886 #define RT5651_DC_CAL_M_MASK (0x1 << 10)
1889 #define RT5651_DC_CAL_M_CAL (0x1 << 10)
1890 #define RT5651_DC_CAL_MASK (0x1 << 9)
1893 #define RT5651_DC_CAL_EN (0x1 << 9)
1896 #define RT5651_HPD_PS_MASK (0x1 << 5)
1899 #define RT5651_HPD_PS_EN (0x1 << 5)
1900 #define RT5651_CAL_M_MASK (0x1 << 4)
1903 #define RT5651_CAL_M_CAL (0x1 << 4)
1904 #define RT5651_CAL_MASK (0x1 << 3)
1907 #define RT5651_CAL_EN (0x1 << 3)
1908 #define RT5651_CAL_TEST_MASK (0x1 << 2)
1911 #define RT5651_CAL_TEST_EN (0x1 << 2)
1915 #define RT5651_CAL_P_CAL (0x1)
1919 #define RT5651_SV_MASK (0x1 << 15)
1922 #define RT5651_SV_EN (0x1 << 15)
1923 #define RT5651_OUT_SV_MASK (0x1 << 13)
1926 #define RT5651_OUT_SV_EN (0x1 << 13)
1927 #define RT5651_HP_SV_MASK (0x1 << 12)
1930 #define RT5651_HP_SV_EN (0x1 << 12)
1931 #define RT5651_ZCD_DIG_MASK (0x1 << 11)
1934 #define RT5651_ZCD_DIG_EN (0x1 << 11)
1935 #define RT5651_ZCD_MASK (0x1 << 10)
1938 #define RT5651_ZCD_PU (0x1 << 10)
1941 #define RT5651_M_ZCD_OM_L (0x1 << 7)
1942 #define RT5651_M_ZCD_OM_R (0x1 << 6)
1943 #define RT5651_M_ZCD_RM_L (0x1 << 5)
1944 #define RT5651_M_ZCD_RM_R (0x1 << 4)
1949 #define RT5651_ZCD_HP_MASK (0x1 << 15)
1952 #define RT5651_ZCD_HP_EN (0x1 << 15)
1955 #define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1958 #define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1959 #define RT5651_CLK_DET_EN (0x1 << 3)
1961 #define RT5651_AMP_DET_EN (0x1 << 1)
1963 #define RT5651_D_GATE_EN (0x1)
1972 #define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1977 #define RT5651_3D_SPK_MASK (0x1 << 15)
1980 #define RT5651_3D_SPK_EN (0x1 << 15)
1989 #define RT5651_WND_MASK (0x1 << 15)
1992 #define RT5651_WND_EN (0x1 << 15)
2015 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2028 #define RT5651_DP_SPK_MASK (0x1 << 10)
2031 #define RT5651_DP_SPK_EN (0x1 << 10)