Lines Matching +full:10 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
99 /* Format - TDM Control */
105 /* Function - Analog */
121 /* Function - Digital */
219 #define RT5645_VOL_L_MUTE (0x1 << 14)
220 #define RT5645_VOL_L_SFT 14
248 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
307 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
308 #define RT5645_STO1_ADC_L_BST_SFT 14
311 #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
312 #define RT5645_STO1_ADC_COMP_SFT 10
315 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
316 #define RT5645_MONO_ADC_L_BST_SFT 14
319 #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
320 #define RT5645_MONO_ADC_COMP_SFT 10
327 #define RT5645_M_ADC_L1 (0x1 << 14)
328 #define RT5645_M_ADC_L1_SFT 14
347 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
348 #define RT5645_M_MONO_ADC_L1_SFT 14
375 #define RT5645_M_DAC1_L (0x1 << 14)
376 #define RT5645_M_DAC1_L_SFT 14
377 #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
378 #define RT5645_DAC1_R_SEL_SFT 10
379 #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
380 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
381 #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
382 #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
395 #define RT5645_M_DAC_L1 (0x1 << 14)
396 #define RT5645_M_DAC_L1_SFT 14
403 #define RT5645_M_ANC_DAC_L (0x1 << 10)
404 #define RT5645_M_ANC_DAC_L_SFT 10
425 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
426 #define RT5645_M_DAC_L1_MONO_L_SFT 14
433 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
434 #define RT5645_M_DAC_R2_MONO_L_SFT 10
453 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
454 #define RT5645_STO_L_DAC_L_VOL_SFT 14
461 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
462 #define RT5645_STO_R_DAC_R_VOL_SFT 10
487 #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
488 #define RT5645_IF2_DAC_SEL_SFT 10
501 #define RT5645_M_PDM1_L (0x1 << 14)
502 #define RT5645_M_PDM1_L_SFT 14
509 #define RT5645_M_PDM2_L (0x1 << 10)
510 #define RT5645_M_PDM2_L_SFT 10
524 #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
525 #define RT5645_G_IN_L_RM_L_SFT 10
536 #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
537 #define RT5645_G_OM_L_RM_L_SFT 10
556 #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
557 #define RT5645_G_IN_R_RM_R_SFT 10
568 #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
569 #define RT5645_G_OM_R_RM_R_SFT 10
600 #define RT5645_M_DAC1_HM (0x1 << 14)
601 #define RT5645_M_DAC1_HM_SFT 14
607 #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
608 #define RT5645_G_RM_L_SM_L_SFT 14
611 #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
612 #define RT5645_G_DAC_L1_SM_L_SFT 10
629 #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
630 #define RT5645_G_RM_R_SM_R_SFT 14
633 #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
634 #define RT5645_G_DAC_R1_SM_R_SFT 10
653 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
654 #define RT5645_M_DAC_R1_SPM_L_SFT 14
673 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
674 #define RT5645_G_MONOMIX_SFT 10
693 #define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
694 #define RT5645_G_BST2_OM_L_SFT 10
705 #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
706 #define RT5645_G_DAC_L2_OM_L_SFT 10
725 #define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
726 #define RT5645_G_BST2_OM_R_SFT 10
737 #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
738 #define RT5645_G_DAC_R2_OM_R_SFT 10
757 #define RT5645_M_DAC_R1_LM (0x1 << 14)
758 #define RT5645_M_DAC_R1_LM_SFT 14
769 #define RT5645_PWR_I2S2 (0x1 << 14)
770 #define RT5645_PWR_I2S2_BIT 14
795 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
796 #define RT5645_PWR_ADC_MF_L_BIT 14
803 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
804 #define RT5645_PWR_DAC_MF_L_BIT 10
819 #define RT5645_PWR_FV1 (0x1 << 14)
820 #define RT5645_PWR_FV1_BIT 14
827 #define RT5645_PWR_MA (0x1 << 10)
828 #define RT5645_PWR_MA_BIT 10
845 #define RT5645_PWR_BST2 (0x1 << 14)
846 #define RT5645_PWR_BST2_BIT 14
853 #define RT5645_PWR_MB2 (0x1 << 10)
854 #define RT5645_PWR_MB2_BIT 10
871 #define RT5645_PWR_OM_R (0x1 << 14)
872 #define RT5645_PWR_OM_R_BIT 14
879 #define RT5645_PWR_RM_R (0x1 << 10)
880 #define RT5645_PWR_RM_R_BIT 10
893 #define RT5645_PWR_SV_R (0x1 << 14)
894 #define RT5645_PWR_SV_R_BIT 14
897 #define RT5645_PWR_HV_R (0x1 << 10)
898 #define RT5645_PWR_HV_R_BIT 10
911 #define RT5645_I2S_O_CP_MASK (0x3 << 10)
912 #define RT5645_I2S_O_CP_SFT 10
913 #define RT5645_I2S_O_CP_OFF (0x0 << 10)
914 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
915 #define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
997 #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
998 #define RT5645_DAC_L_OSR_SFT 14
999 #define RT5645_DAC_L_OSR_128 (0x0 << 14)
1000 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1001 #define RT5645_DAC_L_OSR_32 (0x2 << 14)
1002 #define RT5645_DAC_L_OSR_16 (0x3 << 14)
1011 #define RT5645_ADHPF_EN (0x1 << 10)
1012 #define RT5645_ADHPF_EN_SFT 10
1019 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1020 #define RT5645_DMIC_2_EN_SFT 14
1021 #define RT5645_DMIC_2_DIS (0x0 << 14)
1022 #define RT5645_DMIC_2_EN (0x1 << 14)
1031 #define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1032 #define RT5645_DMIC_2_DP_SFT 10
1033 #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1034 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1035 #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1036 #define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1062 #define RT5645_SCLK_SRC_MASK (0x3 << 14)
1063 #define RT5645_SCLK_SRC_SFT 14
1064 #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1065 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1066 #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1101 #define RT5645_M1_T_MASK (0x1 << 14)
1102 #define RT5645_M1_T_SFT 14
1103 #define RT5645_M1_T_I2S2 (0x0 << 14)
1104 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1147 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1148 #define RT5645_HP_OVCD_SFT 10
1149 #define RT5645_HP_OVCD_DIS (0x0 << 10)
1150 #define RT5645_HP_OVCD_EN (0x1 << 10)
1177 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1178 #define RT5645_CLSD_SCH_SFT 10
1179 #define RT5645_CLSD_SCH_L (0x0 << 10)
1180 #define RT5645_CLSD_SCH_S (0x1 << 10)
1241 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1242 #define RT5645_FAST_UPDN_SFT 10
1243 #define RT5645_FAST_UPDN_DIS (0x0 << 10)
1244 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1285 #define RT5645_SPK_AG_MASK (0x1 << 14)
1286 #define RT5645_SPK_AG_SFT 14
1287 #define RT5645_SPK_AG_DIS (0x0 << 14)
1288 #define RT5645_SPK_AG_EN (0x1 << 14)
1295 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1296 #define RT5645_MIC2_BS_SFT 14
1297 #define RT5645_MIC2_BS_9AV (0x0 << 14)
1298 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1349 #define RT5645_EQ_UPD (0x1 << 14)
1350 #define RT5645_EQ_UPD_BIT 14
1412 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1413 #define RT5645_DRC_AGC_SFT 14
1414 #define RT5645_DRC_AGC_DIS (0x0 << 14)
1415 #define RT5645_DRC_AGC_EN (0x1 << 14)
1468 #define RT5645_ANC_MASK (0x1 << 14)
1469 #define RT5645_ANC_SFT 14
1470 #define RT5645_ANC_DIS (0x0 << 14)
1471 #define RT5645_ANC_EN (0x1 << 14)
1482 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1483 #define RT5645_ANC_CLK_SFT 10
1484 #define RT5645_ANC_CLK_ANC (0x0 << 10)
1485 #define RT5645_ANC_CLK_REG (0x1 << 10)
1535 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1536 #define RT5645_JD_HP_TRG_SFT 10
1537 #define RT5645_JD_HP_TRG_LO (0x0 << 10)
1538 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1607 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1608 #define RT5645_IRQ_OT_SFT 14
1609 #define RT5645_IRQ_OT_BP (0x0 << 14)
1610 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1623 #define RT5645_OT_P_MASK (0x1 << 10)
1624 #define RT5645_OT_P_SFT 10
1625 #define RT5645_OT_P_NOR (0x0 << 10)
1626 #define RT5645_OT_P_INV (0x1 << 10)
1638 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1639 #define RT5645_IRQ_MB2_OC_SFT 14
1640 #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1641 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1668 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1669 #define RT5645_GP2_PIN_SFT 14
1670 #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1671 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1681 #define RT5645_DP_SIG_MASK (0x1 << 10)
1682 #define RT5645_DP_SIG_SFT 10
1683 #define RT5645_DP_SIG_TEST (0x0 << 10)
1684 #define RT5645_DP_SIG_AP (0x1 << 10)
1725 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1726 #define RT5645_GP4_OUT_SFT 10
1727 #define RT5645_GP4_OUT_LO (0x0 << 10)
1728 #define RT5645_GP4_OUT_HI (0x1 << 10)
1777 #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1778 #define RT5645_SEQ2_ST_SFT 10
1779 #define RT5645_SEQ2_ST_RUN (0x0 << 10)
1780 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1827 #define RT5645_SCB_MASK (0x1 << 14)
1828 #define RT5645_SCB_SFT 14
1829 #define RT5645_SCB_DIS (0x0 << 14)
1830 #define RT5645_SCB_EN (0x1 << 14)
1858 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1859 #define RT5645_M_MP3_R_SFT 14
1890 #define RT5645_3D_HP_MASK (0x1 << 14)
1891 #define RT5645_3D_HP_SFT 14
1892 #define RT5645_3D_HP_DIS (0x0 << 14)
1893 #define RT5645_3D_HP_EN (0x1 << 14)
1900 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1901 #define RT5645_3D_HP_M_SFT 10
1902 #define RT5645_3D_HP_M_SUR (0x0 << 10)
1903 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1940 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1941 #define RT5645_DC_CAL_M_SFT 10
1942 #define RT5645_DC_CAL_M_CAL (0x0 << 10)
1943 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1977 #define RT5645_SPO_SV_MASK (0x1 << 14)
1978 #define RT5645_SPO_SV_SFT 14
1979 #define RT5645_SPO_SV_DIS (0x0 << 14)
1980 #define RT5645_SPO_SV_EN (0x1 << 14)
1993 #define RT5645_ZCD_MASK (0x1 << 10)
1994 #define RT5645_ZCD_SFT 10
1995 #define RT5645_ZCD_PD (0x0 << 10)
1996 #define RT5645_ZCD_PU (0x1 << 10)
2038 #define RT5645_WND_FC_NW_MASK (0x3f << 10)
2039 #define RT5645_WND_FC_NW_SFT 10
2058 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2060 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2069 #define RT5645_DP_ATT_MASK (0x3 << 14)
2070 #define RT5645_DP_ATT_SFT 14
2071 #define RT5645_DP_SPK_MASK (0x1 << 10)
2072 #define RT5645_DP_SPK_SFT 10
2073 #define RT5645_DP_SPK_DIS (0x0 << 10)
2074 #define RT5645_DP_SPK_EN (0x1 << 10)
2106 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2107 #define RT5645_IF1_ADC2_IN1_SFT 10