Lines Matching full:dmic
440 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
447 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
454 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
461 SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
467 /* DMIC Source */
477 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
484 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
487 * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
492 * Choose divider parameter that gives the highest possible DMIC frequency in
506 /* find divider that gives DMIC frequency below 3.072MHz */ in rt5514_calc_dmic_clk()
524 dev_err(component->dev, "Failed to set DMIC clock\n"); in rt5514_set_dmic_clk()
570 SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
633 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
635 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
676 { "DMIC1L", NULL, "DMIC CLK" },
677 { "DMIC1R", NULL, "DMIC CLK" },
678 { "DMIC2L", NULL, "DMIC CLK" },
679 { "DMIC2R", NULL, "DMIC CLK" },
681 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
682 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
684 { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
686 { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
730 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
731 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
733 { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
735 { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
1229 device_property_read_u32(dev, "realtek,dmic-init-delay-ms", in rt5514_parse_dp()