33 #define RT1305_PR_RANGE_BASE (0xff + 1)
34 #define RT1305_PR_SPACING 0x100
36 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
43 		.range_max = RT1305_PR_BASE + 0xff,
45 		.selector_mask = 0xff,
46 		.selector_shift = 0x0,
48 		.window_len = 0x1,
55 	{ RT1305_PR_BASE + 0xcf, 0x5548 },
56 	{ RT1305_PR_BASE + 0x5d, 0x0442 },
57 	{ RT1305_PR_BASE + 0xc1, 0x0320 },
59 	{ RT1305_POWER_STATUS, 0x0000 },
61 	{ RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
62 	{ RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
63 	{ RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
65 	{ RT1305_DAC_SET_1, 0xdfdf },	/* 4 ohm 2W  */
66 	{ RT1305_ADC_SET_3, 0x0219 },
67 	{ RT1305_ADC_SET_1, 0x170f },	/* 0.2 ohm RSense*/
89 	{ 0x04, 0x0400 },
90 	{ 0x05, 0x0880 },
91 	{ 0x06, 0x0000 },
92 	{ 0x07, 0x3100 },
93 	{ 0x08, 0x8000 },
94 	{ 0x09, 0x0000 },
95 	{ 0x0a, 0x087e },
96 	{ 0x0b, 0x0020 },
97 	{ 0x0c, 0x0802 },
98 	{ 0x0d, 0x0020 },
99 	{ 0x10, 0x1d1d },
100 	{ 0x11, 0x1d1d },
101 	{ 0x12, 0xffff },
102 	{ 0x14, 0x000c },
103 	{ 0x16, 0x1717 },
104 	{ 0x17, 0x4000 },
105 	{ 0x18, 0x0019 },
106 	{ 0x20, 0x0000 },
107 	{ 0x22, 0x0000 },
108 	{ 0x24, 0x0000 },
109 	{ 0x26, 0x0000 },
110 	{ 0x28, 0x0000 },
111 	{ 0x2a, 0x4000 },
112 	{ 0x2b, 0x3000 },
113 	{ 0x2d, 0x6000 },
114 	{ 0x2e, 0x0000 },
115 	{ 0x2f, 0x8000 },
116 	{ 0x32, 0x0000 },
117 	{ 0x39, 0x0001 },
118 	{ 0x3a, 0x0000 },
119 	{ 0x3b, 0x1020 },
120 	{ 0x3c, 0x0000 },
121 	{ 0x3d, 0x0000 },
122 	{ 0x3e, 0x4c00 },
123 	{ 0x3f, 0x3000 },
124 	{ 0x40, 0x000c },
125 	{ 0x42, 0x0400 },
126 	{ 0x46, 0xc22c },
127 	{ 0x47, 0x0000 },
128 	{ 0x4b, 0x0000 },
129 	{ 0x4c, 0x0300 },
130 	{ 0x4f, 0xf000 },
131 	{ 0x50, 0xc200 },
132 	{ 0x51, 0x1f1f },
133 	{ 0x52, 0x01f0 },
134 	{ 0x53, 0x407f },
135 	{ 0x54, 0xffff },
136 	{ 0x58, 0x4005 },
137 	{ 0x5e, 0x0000 },
138 	{ 0x5f, 0x0000 },
139 	{ 0x60, 0xee13 },
140 	{ 0x62, 0x0000 },
141 	{ 0x63, 0x5f5f },
142 	{ 0x64, 0x0040 },
143 	{ 0x65, 0x4000 },
144 	{ 0x66, 0x4004 },
145 	{ 0x67, 0x0306 },
146 	{ 0x68, 0x8c04 },
147 	{ 0x69, 0xe021 },
148 	{ 0x6a, 0x0000 },
149 	{ 0x6c, 0xaaaa },
150 	{ 0x70, 0x0333 },
151 	{ 0x71, 0x3330 },
152 	{ 0x72, 0x3333 },
153 	{ 0x73, 0x3300 },
154 	{ 0x74, 0x0000 },
155 	{ 0x75, 0x0000 },
156 	{ 0x76, 0x0000 },
157 	{ 0x7a, 0x0003 },
158 	{ 0x7c, 0x10ec },
159 	{ 0x7e, 0x6251 },
160 	{ 0x80, 0x0800 },
161 	{ 0x81, 0x4000 },
162 	{ 0x82, 0x0000 },
163 	{ 0x90, 0x7a01 },
164 	{ 0x91, 0x8431 },
165 	{ 0x92, 0x0180 },
166 	{ 0x93, 0x0000 },
167 	{ 0x94, 0x0000 },
168 	{ 0x95, 0x0000 },
169 	{ 0x96, 0x0000 },
170 	{ 0x97, 0x0000 },
171 	{ 0x98, 0x0000 },
172 	{ 0x99, 0x0000 },
173 	{ 0x9a, 0x0000 },
174 	{ 0x9b, 0x0000 },
175 	{ 0x9c, 0x0000 },
176 	{ 0x9d, 0x0000 },
177 	{ 0x9e, 0x0000 },
178 	{ 0x9f, 0x0000 },
179 	{ 0xa0, 0x0000 },
180 	{ 0xb0, 0x8200 },
181 	{ 0xb1, 0x00ff },
182 	{ 0xb2, 0x0008 },
183 	{ 0xc0, 0x0200 },
184 	{ 0xc1, 0x0000 },
185 	{ 0xc2, 0x0000 },
186 	{ 0xc3, 0x0000 },
187 	{ 0xc4, 0x0000 },
188 	{ 0xc5, 0x0000 },
189 	{ 0xc6, 0x0000 },
190 	{ 0xc7, 0x0000 },
191 	{ 0xc8, 0x0000 },
192 	{ 0xc9, 0x0000 },
193 	{ 0xca, 0x0200 },
194 	{ 0xcb, 0x0000 },
195 	{ 0xcc, 0x0000 },
196 	{ 0xcd, 0x0000 },
197 	{ 0xce, 0x0000 },
198 	{ 0xcf, 0x0000 },
199 	{ 0xd0, 0x0000 },
200 	{ 0xd1, 0x0000 },
201 	{ 0xd2, 0x0000 },
202 	{ 0xd3, 0x0000 },
203 	{ 0xd4, 0x0200 },
204 	{ 0xd5, 0x0000 },
205 	{ 0xd6, 0x0000 },
206 	{ 0xd7, 0x0000 },
207 	{ 0xd8, 0x0000 },
208 	{ 0xd9, 0x0000 },
209 	{ 0xda, 0x0000 },
210 	{ 0xdb, 0x0000 },
211 	{ 0xdc, 0x0000 },
212 	{ 0xdd, 0x0000 },
213 	{ 0xde, 0x0200 },
214 	{ 0xdf, 0x0000 },
215 	{ 0xe0, 0x0000 },
216 	{ 0xe1, 0x0000 },
217 	{ 0xe2, 0x0000 },
218 	{ 0xe3, 0x0000 },
219 	{ 0xe4, 0x0000 },
220 	{ 0xe5, 0x0000 },
221 	{ 0xe6, 0x0000 },
222 	{ 0xe7, 0x0000 },
223 	{ 0xe8, 0x0200 },
224 	{ 0xe9, 0x0000 },
225 	{ 0xea, 0x0000 },
226 	{ 0xeb, 0x0000 },
227 	{ 0xec, 0x0000 },
228 	{ 0xed, 0x0000 },
229 	{ 0xee, 0x0000 },
230 	{ 0xef, 0x0000 },
231 	{ 0xf0, 0x0000 },
232 	{ 0xf1, 0x0000 },
233 	{ 0xf2, 0x0200 },
234 	{ 0xf3, 0x0000 },
235 	{ 0xf4, 0x0000 },
236 	{ 0xf5, 0x0000 },
237 	{ 0xf6, 0x0000 },
238 	{ 0xf7, 0x0000 },
239 	{ 0xf8, 0x0000 },
240 	{ 0xf9, 0x0000 },
241 	{ 0xfa, 0x0000 },
242 	{ 0xfb, 0x0000 },
250 	return 0;  in rt1305_reg_init()
257 	for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {  in rt1305_volatile_register()
309 	for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {  in rt1305_readable_register()
381 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
395 	regmap_write(regmap, RT1305_RESET, 0);  in rt1305_reset()
400 			8, 0, 0xff, 0, dac_vol_tlv),
420 		return 0;  in rt1305_is_rc_clk_from_pll()
433 		return 0;  in rt1305_is_sys_clk_from_pll()
449 			RT1305_POW_PDB_JD_MASK, 0);  in rt1305_classd_event()
454 		return 0;  in rt1305_classd_event()
457 	return 0;  in rt1305_classd_event()
470 		RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
472 		RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
474 		RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
476 		RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
478 		RT1305_POW_LDO2_BIT, 0, NULL, 0),
480 		RT1305_POW_BG2_BIT, 0, NULL, 0),
482 		RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
484 		RT1305_POW_VREF_BIT, 0, NULL, 0),
486 		RT1305_POW_VREF1_BIT, 0, NULL, 0),
488 		RT1305_POW_VREF2_BIT, 0, NULL, 0),
492 		RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
494 		RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
496 		RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
498 		RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
500 		RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
502 		RT1305_POW_CLAMP_BIT, 0, NULL, 0),
504 		RT1305_POW_BUFL_BIT, 0, NULL, 0),
506 		RT1305_POW_BUFR_BIT, 0, NULL, 0),
508 		RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
510 		RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
512 		RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
514 		RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
516 		RT1305_POR_AVDD1_BIT, 0, NULL, 0),
518 		RT1305_POR_AVDD2_BIT, 0, NULL, 0),
522 		RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
524 		RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
526 		RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
528 		RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
530 		RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
532 		RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
534 		RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
538 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
542 		RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
544 		RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
545 	SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
546 	SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
547 	SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
550 	SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
614 	if (sclk <= 0 || rate <= 0)  in rt1305_get_clk_info()
618 	for (i = 0; i < ARRAY_SIZE(pd); i++)  in rt1305_get_clk_info()
630 	unsigned int val_len = 0, val_clk, mask_clk;  in rt1305_hw_params()
635 	if (pre_div < 0) {  in rt1305_hw_params()
637 		snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,  in rt1305_hw_params()
641 		pre_div = 0;  in rt1305_hw_params()
644 	if (frame_size < 0) {  in rt1305_hw_params()
692 	return 0;  in rt1305_hw_params()
699 	unsigned int reg_val = 0, reg1_val = 0;  in rt1305_set_dai_fmt()
708 		rt1305->master = 0;  in rt1305_set_dai_fmt()
752 	return 0;  in rt1305_set_dai_fmt()
759 	unsigned int reg_val = 0;  in rt1305_set_component_sysclk()
762 		return 0;  in rt1305_set_component_sysclk()
789 	return 0;  in rt1305_set_component_sysclk()
802 		return 0;  in rt1305_set_component_pll()
807 		rt1305->pll_in = 0;  in rt1305_set_component_pll()
808 		rt1305->pll_out = 0;  in rt1305_set_component_pll()
812 		return 0;  in rt1305_set_component_pll()
843 	if (ret < 0) {  in rt1305_set_component_pll()
849 		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),  in rt1305_set_component_pll()
853 		((pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT) |  in rt1305_set_component_pll()
863 	return 0;  in rt1305_set_component_pll()
875 	return 0;  in rt1305_probe()
893 	return 0;  in rt1305_suspend()
903 	return 0;  in rt1305_resume()
978 	{"10EC1305", 0,},
979 	{"10EC1306", 0,},
986 	{ "rt1305", 0 },
987 	{ "rt1306", 0 },
1001 	regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);  in rt1305_calibrate()
1002 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);  in rt1305_calibrate()
1003 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);  in rt1305_calibrate()
1004 	regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);  in rt1305_calibrate()
1005 	regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);  in rt1305_calibrate()
1006 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);  in rt1305_calibrate()
1007 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);  in rt1305_calibrate()
1008 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);  in rt1305_calibrate()
1009 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);  in rt1305_calibrate()
1012 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);  in rt1305_calibrate()
1014 	regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);  in rt1305_calibrate()
1015 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);  in rt1305_calibrate()
1016 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);  in rt1305_calibrate()
1017 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);  in rt1305_calibrate()
1018 	regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);  in rt1305_calibrate()
1019 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);  in rt1305_calibrate()
1020 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);  in rt1305_calibrate()
1021 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);  in rt1305_calibrate()
1022 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);  in rt1305_calibrate()
1023 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);  in rt1305_calibrate()
1024 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);  in rt1305_calibrate()
1027 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);  in rt1305_calibrate()
1028 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);  in rt1305_calibrate()
1029 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);  in rt1305_calibrate()
1030 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);  in rt1305_calibrate()
1031 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);  in rt1305_calibrate()
1032 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);  in rt1305_calibrate()
1033 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);  in rt1305_calibrate()
1034 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);  in rt1305_calibrate()
1042 	pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);  in rt1305_calibrate()
1045 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);  in rt1305_calibrate()
1046 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);  in rt1305_calibrate()
1047 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);  in rt1305_calibrate()
1048 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);  in rt1305_calibrate()
1049 	regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);  in rt1305_calibrate()
1050 	regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);  in rt1305_calibrate()
1052 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);  in rt1305_calibrate()
1053 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);  in rt1305_calibrate()
1054 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);  in rt1305_calibrate()
1055 	regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);  in rt1305_calibrate()
1056 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);  in rt1305_calibrate()
1057 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);  in rt1305_calibrate()
1059 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);  in rt1305_calibrate()
1060 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);  in rt1305_calibrate()
1064 	pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);  in rt1305_calibrate()
1068 	if (rhl != 0)  in rt1305_calibrate()
1070 	pr_debug("Left_r0 = 0x%llx\n", r0l);  in rt1305_calibrate()
1072 	regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);  in rt1305_calibrate()
1073 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);  in rt1305_calibrate()
1074 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);  in rt1305_calibrate()
1076 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);  in rt1305_calibrate()
1077 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);  in rt1305_calibrate()
1081 	pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);  in rt1305_calibrate()
1085 	if (rhl != 0)  in rt1305_calibrate()
1087 	pr_debug("Right_r0 = 0x%llx\n", r0r);  in rt1305_calibrate()
1089 	regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);  in rt1305_calibrate()
1093 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,  in rt1305_calibrate()
1094 			(r0l >> 16) & 0xffff);  in rt1305_calibrate()
1095 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,  in rt1305_calibrate()
1096 			r0l & 0xffff);  in rt1305_calibrate()
1097 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,  in rt1305_calibrate()
1098 			((r0r >> 16) & 0xffff) | 0xf800);  in rt1305_calibrate()
1099 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,  in rt1305_calibrate()
1100 			r0r & 0xffff);  in rt1305_calibrate()
1106 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);  in rt1305_calibrate()
1108 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);  in rt1305_calibrate()
1109 	regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);  in rt1305_calibrate()
1110 	regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);  in rt1305_calibrate()
1111 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);  in rt1305_calibrate()
1112 	regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);  in rt1305_calibrate()
1113 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);  in rt1305_calibrate()
1114 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);  in rt1305_calibrate()