1 // SPDX-License-Identifier: GPL-2.0
3 // nau8822.c  --  NAU8822 ALSA Soc Audio driver
8 // Co-author: John Hsu <kchsu0@nuvoton.com>
9 // Co-author: Seven Li <wtli@nuvoton.com>
184 	struct soc_bytes_ext *params = (void *)kcontrol->private_value;  in nau8822_eq_get()
188 	val = (u16 *)ucontrol->value.bytes.data;  in nau8822_eq_get()
190 	for (i = 0; i < params->max / sizeof(u16); i++) {  in nau8822_eq_get()
192 		/* conversion of 16-bit integers between native CPU format  in nau8822_eq_get()
204  * cut-off frequency, bandwidth control, and equalizer path.
215 	struct soc_bytes_ext *params = (void *)kcontrol->private_value;  in nau8822_eq_put()
220 	data = kmemdup(ucontrol->value.bytes.data,  in nau8822_eq_put()
221 		params->max, GFP_KERNEL | GFP_DMA);  in nau8822_eq_put()
223 		return -ENOMEM;  in nau8822_eq_put()
227 	for (i = 0; i < params->max / sizeof(u16); i++) {  in nau8822_eq_put()
228 		/* conversion of 16-bit integers between native CPU format  in nau8822_eq_put()
234 			dev_err(component->dev,  in nau8822_eq_put()
247 	"Off", "NC", "u-law", "A-law"};
274 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
275 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
276 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
278 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
445 		snd_soc_dapm_to_component(source->dapm);  in check_mclk_select_pll()
615 	struct snd_soc_component *component = dai->component;  in nau8822_set_dai_sysclk()
618 	nau8822->div_id = clk_id;  in nau8822_set_dai_sysclk()
619 	nau8822->sysclk = freq;  in nau8822_set_dai_sysclk()
620 	dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,  in nau8822_set_dai_sysclk()
621 		clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");  in nau8822_set_dai_sysclk()
633 		return -EINVAL;  in nau8822_calc_pll()
647 		return -EINVAL;  in nau8822_calc_pll()
648 	pll_param->mclk_scaler = scal_sel;  in nau8822_calc_pll()
651 	/* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional  in nau8822_calc_pll()
655 	pll_param->pre_factor = 0;  in nau8822_calc_pll()
658 		pll_param->pre_factor = 1;  in nau8822_calc_pll()
660 	pll_param->pll_int = (pll_ratio >> 28) & 0xF;  in nau8822_calc_pll()
661 	pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);  in nau8822_calc_pll()
668 	struct snd_soc_component *component = dai->component;  in nau8822_config_clkdiv()
670 	struct nau8822_pll *pll = &nau8822->pll;  in nau8822_config_clkdiv()
673 	switch (nau8822->div_id) {  in nau8822_config_clkdiv()
677 		 * and large or equal to IMCLK.  in nau8822_config_clkdiv()
682 			sclk = (nau8822->sysclk * 10) /	nau8822_mclk_scaler[i];  in nau8822_config_clkdiv()
687 		dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",  in nau8822_config_clkdiv()
690 		/* master clock from MCLK and disable PLL */  in nau8822_config_clkdiv()
701 		if (pll->mclk_scaler != div) {  in nau8822_config_clkdiv()
702 			dev_err(component->dev,  in nau8822_config_clkdiv()
704 			return -EINVAL;  in nau8822_config_clkdiv()
715 		return -EINVAL;  in nau8822_config_clkdiv()
724 	struct snd_soc_component *component = dai->component;  in nau8822_set_pll()
726 	struct nau8822_pll *pll_param = &nau8822->pll;  in nau8822_set_pll()
729 	if (freq_in == pll_param->freq_in &&  in nau8822_set_pll()
730 	    freq_out == pll_param->freq_out)  in nau8822_set_pll()
734 		dev_dbg(component->dev, "PLL disabled\n");  in nau8822_set_pll()
744 		dev_err(component->dev, "Unsupported input clock %d\n",  in nau8822_set_pll()
749 	dev_info(component->dev,  in nau8822_set_pll()
751 		pll_param->pll_int, pll_param->pll_frac,  in nau8822_set_pll()
752 		pll_param->mclk_scaler, pll_param->pre_factor);  in nau8822_set_pll()
758 		(pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |  in nau8822_set_pll()
759 		pll_param->pll_int);  in nau8822_set_pll()
761 		NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &  in nau8822_set_pll()
764 		NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &  in nau8822_set_pll()
767 		NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);  in nau8822_set_pll()
770 		pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);  in nau8822_set_pll()
776 	pll_param->freq_in = freq_in;  in nau8822_set_pll()
777 	pll_param->freq_out = freq_out;  in nau8822_set_pll()
784 	struct snd_soc_component *component = dai->component;  in nau8822_set_dai_fmt()
787 	dev_dbg(component->dev, "%s\n", __func__);  in nau8822_set_dai_fmt()
797 		return -EINVAL;  in nau8822_set_dai_fmt()
813 		return -EINVAL;  in nau8822_set_dai_fmt()
829 		return -EINVAL;  in nau8822_set_dai_fmt()
846 	struct snd_soc_component *component = dai->component;  in nau8822_hw_params()
851 	/* make BCLK and LRC divide configuration if the codec as master. */  in nau8822_hw_params()
854 		/* get the bclk and fs ratio */  in nau8822_hw_params()
863 			return -EINVAL;  in nau8822_hw_params()
881 		return -EINVAL;  in nau8822_hw_params()
904 		return -EINVAL;  in nau8822_hw_params()
912 	/* If the master clock is from MCLK, provide the runtime FS for driver  in nau8822_hw_params()
915 	if (nau8822->div_id == NAU8822_CLK_MCLK)  in nau8822_hw_params()
923 	struct snd_soc_component *component = dai->component;  in nau8822_mute()
925 	dev_dbg(component->dev, "%s: %d\n", __func__, mute);  in nau8822_mute()
976 	dev_dbg(component->dev, "%s: %d\n", __func__, level);  in nau8822_set_bias_level()
996 	.name = "nau8822-hifi",
1021 	regcache_mark_dirty(nau8822->regmap);  in nau8822_suspend()
1030 	regcache_sync(nau8822->regmap);  in nau8822_resume()
1038  * These registers contain an "update" bit - bit 8. This means, for example,
1040  * the update bit is set, will also the volume be updated - simultaneously for
1105 	struct device *dev = &i2c->dev;  in nau8822_i2c_probe()
1112 			return -ENOMEM;  in nau8822_i2c_probe()
1116 	nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);  in nau8822_i2c_probe()
1117 	if (IS_ERR(nau8822->regmap)) {  in nau8822_i2c_probe()
1118 		ret = PTR_ERR(nau8822->regmap);  in nau8822_i2c_probe()
1119 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);  in nau8822_i2c_probe()
1122 	nau8822->dev = dev;  in nau8822_i2c_probe()
1125 	ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);  in nau8822_i2c_probe()
1127 		dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);  in nau8822_i2c_probe()
1134 		dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);  in nau8822_i2c_probe()