1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
39 	{ 1, 0x0 },
40 	{ 2, 0x2 },
41 	{ 4, 0x3 },
42 	{ 8, 0x4 },
43 	{ 16, 0x5 },
44 	{ 32, 0x6 },
45 	{ 3, 0x7 },
46 	{ 6, 0xa },
47 	{ 12, 0xb },
48 	{ 24, 0xc },
53 	{ 512000, 0x01 },
54 	{ 256000, 0x02 },
55 	{ 128000, 0x04 },
56 	{ 64000, 0x08 },
57 	{ 32000, 0x10 },
58 	{ 8000, 0x20 },
59 	{ 4000, 0x40 },
63 	{ 1, 0x0 },
64 	{ 2, 0x1 },
65 	{ 4, 0x2 },
66 	{ 8, 0x3 },
74 	{ 256, 0 },	/* OSR 256, SRC 1 */
78 	{NAU8540_REG_POWER_MANAGEMENT, 0x0000},
79 	{NAU8540_REG_CLOCK_CTRL, 0x0000},
80 	{NAU8540_REG_CLOCK_SRC, 0x0000},
81 	{NAU8540_REG_FLL1, 0x0001},
82 	{NAU8540_REG_FLL2, 0x3126},
83 	{NAU8540_REG_FLL3, 0x0008},
84 	{NAU8540_REG_FLL4, 0x0010},
85 	{NAU8540_REG_FLL5, 0xC000},
86 	{NAU8540_REG_FLL6, 0x6000},
87 	{NAU8540_REG_FLL_VCO_RSV, 0xF13C},
88 	{NAU8540_REG_PCM_CTRL0, 0x000B},
89 	{NAU8540_REG_PCM_CTRL1, 0x3010},
90 	{NAU8540_REG_PCM_CTRL2, 0x0800},
91 	{NAU8540_REG_PCM_CTRL3, 0x0000},
92 	{NAU8540_REG_PCM_CTRL4, 0x000F},
93 	{NAU8540_REG_ALC_CONTROL_1, 0x0000},
94 	{NAU8540_REG_ALC_CONTROL_2, 0x700B},
95 	{NAU8540_REG_ALC_CONTROL_3, 0x0022},
96 	{NAU8540_REG_ALC_CONTROL_4, 0x1010},
97 	{NAU8540_REG_ALC_CONTROL_5, 0x1010},
98 	{NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
99 	{NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
100 	{NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
101 	{NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
102 	{NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
103 	{NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
104 	{NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
105 	{NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
106 	{NAU8540_REG_HPF_FILTER_CH12, 0x0000},
107 	{NAU8540_REG_HPF_FILTER_CH34, 0x0000},
108 	{NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
109 	{NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
110 	{NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
111 	{NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
112 	{NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
113 	{NAU8540_REG_DIGITAL_MUX, 0x00E4},
114 	{NAU8540_REG_GPIO_CTRL, 0x0000},
115 	{NAU8540_REG_MISC_CTRL, 0x0000},
116 	{NAU8540_REG_I2C_CTRL, 0xEFFF},
117 	{NAU8540_REG_VMID_CTRL, 0x0000},
118 	{NAU8540_REG_MUTE, 0x0000},
119 	{NAU8540_REG_ANALOG_ADC1, 0x0011},
120 	{NAU8540_REG_ANALOG_ADC2, 0x0020},
121 	{NAU8540_REG_ANALOG_PWR, 0x0000},
122 	{NAU8540_REG_MIC_BIAS, 0x0004},
123 	{NAU8540_REG_REFERENCE, 0x0000},
124 	{NAU8540_REG_FEPGA1, 0x0000},
125 	{NAU8540_REG_FEPGA2, 0x0000},
126 	{NAU8540_REG_FEPGA3, 0x0101},
127 	{NAU8540_REG_FEPGA4, 0x0101},
128 	{NAU8540_REG_PWR, 0x0000},
183 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
184 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
188 		0, 0x520, 0, adc_vol_tlv),
190 		0, 0x520, 0, adc_vol_tlv),
192 		0, 0x520, 0, adc_vol_tlv),
194 		0, 0x520, 0, adc_vol_tlv),
197 		0, 0x25, 0, fepga_gain_tlv),
199 		8, 0x25, 0, fepga_gain_tlv),
201 		0, 0x25, 0, fepga_gain_tlv),
203 		8, 0x25, 0, fepga_gain_tlv),
219 	SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
228 	digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
236 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in adc_power_control()
242 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in adc_power_control()
243 			NAU8540_I2S_DO12_TRI, 0);  in adc_power_control()
244 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in adc_power_control()
245 			NAU8540_I2S_DO34_TRI, 0);  in adc_power_control()
247 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in adc_power_control()
249 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in adc_power_control()
252 	return 0;  in adc_power_control()
258 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in aiftx_power_control()
262 		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);  in aiftx_power_control()
263 		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);  in aiftx_power_control()
265 	return 0;  in aiftx_power_control()
269 	SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
270 	SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
277 	SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
278 	SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
279 	SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
280 	SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
283 		NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
286 		NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
289 		NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
292 		NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
295 	SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
296 	SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
297 	SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
298 	SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
301 		SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
302 	SND_SOC_DAPM_MUX("Digital CH3 Mux",
303 		SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
305 		SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
307 		SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
309 	SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
326 	{"ADC CH3", NULL, "ADC3"},
336 	{"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
341 	{"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
344 	{"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
345 	{"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
346 	{"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
347 	{"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
351 	{"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
356 	{"AIFTX", NULL, "Digital CH3 Mux"},
365 	regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);  in nau8540_get_osr()
375 	struct snd_soc_component *component = dai->component;  in nau8540_dai_startup()
380 	if (!osr || !osr->osr)  in nau8540_dai_startup()
381 		return -EINVAL;  in nau8540_dai_startup()
383 	return snd_pcm_hw_constraint_minmax(substream->runtime,  in nau8540_dai_startup()
385 					    0, CLK_ADC_MAX / osr->osr);  in nau8540_dai_startup()
391 	struct snd_soc_component *component = dai->component;  in nau8540_hw_params()
393 	unsigned int val_len = 0;  in nau8540_hw_params()
403 	if (!osr || !osr->osr)  in nau8540_hw_params()
404 		return -EINVAL;  in nau8540_hw_params()
405 	if (params_rate(params) * osr->osr > CLK_ADC_MAX)  in nau8540_hw_params()
406 		return -EINVAL;  in nau8540_hw_params()
407 	regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_hw_params()
409 		osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);  in nau8540_hw_params()
425 		return -EINVAL;  in nau8540_hw_params()
428 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,  in nau8540_hw_params()
431 	return 0;  in nau8540_hw_params()
436 	struct snd_soc_component *component = dai->component;  in nau8540_set_fmt()
438 	unsigned int ctrl1_val = 0, ctrl2_val = 0;  in nau8540_set_fmt()
447 		return -EINVAL;  in nau8540_set_fmt()
457 		return -EINVAL;  in nau8540_set_fmt()
478 		return -EINVAL;  in nau8540_set_fmt()
481 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,  in nau8540_set_fmt()
484 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in nau8540_set_fmt()
486 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in nau8540_set_fmt()
487 		NAU8540_I2S_DO34_OE, 0);  in nau8540_set_fmt()
489 	return 0;  in nau8540_set_fmt()
493  * nau8540_set_tdm_slot - configure DAI TX TDM.
496  *                 0xf for normal 4 channel TDM.
497  *                 0xf0 for shifted 4 channel TDM
507 	struct snd_soc_component *component = dai->component;  in nau8540_set_tdm_slot()
509 	unsigned int ctrl2_val = 0, ctrl4_val = 0;  in nau8540_set_tdm_slot()
511 	if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))  in nau8540_set_tdm_slot()
512 		return -EINVAL;  in nau8540_set_tdm_slot()
515 	if (tx_mask & 0xf0) {  in nau8540_set_tdm_slot()
521 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,  in nau8540_set_tdm_slot()
524 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in nau8540_set_tdm_slot()
526 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in nau8540_set_tdm_slot()
530 	return 0;  in nau8540_set_tdm_slot()
546 	.name = "nau8540-hifi",
558  * nau8540_calc_fll_param - Calculate FLL parameters.
565  * Returns 0 for success or negative error code.
574 	 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.  in nau8540_calc_fll_param()
577 	for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {  in nau8540_calc_fll_param()
583 		return -EINVAL;  in nau8540_calc_fll_param()
584 	fll_param->clk_ref_div = fll_pre_scalar[i].val;  in nau8540_calc_fll_param()
587 	for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {  in nau8540_calc_fll_param()
592 		return -EINVAL;  in nau8540_calc_fll_param()
593 	fll_param->ratio = fll_ratio[i].val;  in nau8540_calc_fll_param()
596 	 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be  in nau8540_calc_fll_param()
600 	fvco_max = 0;  in nau8540_calc_fll_param()
602 	for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {  in nau8540_calc_fll_param()
611 		return -EINVAL;  in nau8540_calc_fll_param()
612 	fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;  in nau8540_calc_fll_param()
614 	/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional  in nau8540_calc_fll_param()
617 	fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);  in nau8540_calc_fll_param()
618 	fll_param->fll_int = (fvco >> 16) & 0x3FF;  in nau8540_calc_fll_param()
619 	fll_param->fll_frac = fvco & 0xFFFF;  in nau8540_calc_fll_param()
620 	return 0;  in nau8540_calc_fll_param()
628 		NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);  in nau8540_fll_apply()
631 		fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));  in nau8540_fll_apply()
632 	/* FLL 16-bit fractional input */  in nau8540_fll_apply()
633 	regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);  in nau8540_fll_apply()
634 	/* FLL 10-bit integer input */  in nau8540_fll_apply()
636 		NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);  in nau8540_fll_apply()
637 	/* FLL pre-scaler */  in nau8540_fll_apply()
640 		fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);  in nau8540_fll_apply()
644 		NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);  in nau8540_fll_apply()
645 	if (fll_param->fll_frac) {  in nau8540_fll_apply()
659 			NAU8540_SDM_EN | NAU8540_CUTOFF500, 0);  in nau8540_fll_apply()
673 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
675 			NAU8540_FLL_CLK_SRC_MCLK | 0);  in nau8540_set_pll()
679 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
682 			(0xf << NAU8540_GAIN_ERR_SFT));  in nau8540_set_pll()
686 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
689 			(0xf << NAU8540_GAIN_ERR_SFT));  in nau8540_set_pll()
693 		dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);  in nau8540_set_pll()
694 		return -EINVAL;  in nau8540_set_pll()
696 	dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",  in nau8540_set_pll()
701 	if (ret < 0) {  in nau8540_set_pll()
702 		dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);  in nau8540_set_pll()
705 	dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",  in nau8540_set_pll()
709 	nau8540_fll_apply(nau8540->regmap, &fll_param);  in nau8540_set_pll()
711 	regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_pll()
714 	return 0;  in nau8540_set_pll()
725 		regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_sysclk()
727 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,  in nau8540_set_sysclk()
728 			NAU8540_DCO_EN, 0);  in nau8540_set_sysclk()
732 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,  in nau8540_set_sysclk()
734 		regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_sysclk()
739 		dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);  in nau8540_set_sysclk()
740 		return -EINVAL;  in nau8540_set_sysclk()
743 	dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",  in nau8540_set_sysclk()
746 	return 0;  in nau8540_set_sysclk()
751 	regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);  in nau8540_reset_chip()
752 	regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);  in nau8540_reset_chip()
757 	struct regmap *regmap = nau8540->regmap;  in nau8540_init_regs()
762 		NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));  in nau8540_init_regs()
796 	regcache_cache_only(nau8540->regmap, true);  in nau8540_suspend()
797 	regcache_mark_dirty(nau8540->regmap);  in nau8540_suspend()
799 	return 0;  in nau8540_suspend()
806 	regcache_cache_only(nau8540->regmap, false);  in nau8540_resume()
807 	regcache_sync(nau8540->regmap);  in nau8540_resume()
809 	return 0;  in nau8540_resume()
845 	struct device *dev = &i2c->dev;  in nau8540_i2c_probe()
852 			return -ENOMEM;  in nau8540_i2c_probe()
856 	nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);  in nau8540_i2c_probe()
857 	if (IS_ERR(nau8540->regmap))  in nau8540_i2c_probe()
858 		return PTR_ERR(nau8540->regmap);  in nau8540_i2c_probe()
859 	ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);  in nau8540_i2c_probe()
860 	if (ret < 0) {  in nau8540_i2c_probe()
866 	nau8540->dev = dev;  in nau8540_i2c_probe()
867 	nau8540_reset_chip(nau8540->regmap);  in nau8540_i2c_probe()
875 	{ "nau8540", 0 },