Lines Matching +full:0 +full:x2140
23 #define RG_CLKSQ_EN_AUD_BIT (0)
32 #define RG_AUDDACLPWRUP_VAUDP32_BIT (0)
43 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK (0x3)
46 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK (0x3)
49 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK (0x3)
62 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK (0x3)
86 #define RG_AFE_ON_BIT (0)
89 #define RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT (0)
92 #define UL_SRC_ON_TMP_CTL (0)
95 #define RG_DL_SINE_ON_SFT (0)
96 #define RG_DL_SINE_ON_MASK (0x1)
99 #define RG_UL_SINE_ON_MASK (0x1)
102 #define AUD_TOP_PDN_RESERVED_BIT 0
113 #define RG_NCP_ON_BIT 0
124 #define RG_AUDPREAMPLON 0
129 #define RG_AUDPREAMPLINPUTSEL_MASK (0x3)
134 #define RG_AUDADCLINPUTSEL_MASK (0x3)
137 #define RG_AUDPREAMPRON 0
142 #define RG_AUDPREAMPRINPUTSEL_MASK (0x3)
147 #define RG_AUDADCRINPUTSEL_MASK (0x3)
153 #define RG_AUDPWDBMICBIAS0 0
162 #define RG_AUDPWDBMICBIAS1 0
203 0x1f << 7, 0x8 << 7); in set_hp_gain_zero()
205 0x1f << 0, 0x8 << 0); in set_hp_gain_zero()
213 return 0; in get_cap_reg_val()
236 return 0; in get_play_reg_val()
278 return 0; in mt6351_codec_dai_hw_params()
328 idx = 8; /* 0dB */ in hp_gain_ramp_set()
332 old_idx = 8; /* 0dB */ in hp_gain_ramp_set()
344 while (offset > 0) { in hp_gain_ramp_set()
348 if ((reg_idx >= 0 && reg_idx <= 0x12) || reg_idx == 0x1f) { in hp_gain_ramp_set()
351 0xf9f, in hp_gain_ramp_set()
363 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 8, 0x1 << 8); in hp_zcd_enable()
364 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 7, 0x0 << 7); in hp_zcd_enable()
366 /* timeout, 1=5ms, 0=30ms */ in hp_zcd_enable()
367 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 6, 0x1 << 6); in hp_zcd_enable()
369 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x3 << 4, 0x0 << 4); in hp_zcd_enable()
370 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x7 << 1, 0x5 << 1); in hp_zcd_enable()
371 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON0, 0x1 << 0, 0x1 << 0); in hp_zcd_enable()
376 regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000); in hp_zcd_disable()
379 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
380 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
385 MT6351_ZCD_CON2, 0, 7, 0x12, 1,
388 MT6351_ZCD_CON1, 0, 7, 0x12, 1,
391 MT6351_ZCD_CON3, 0, 0x12, 1,
396 8, 4, 0,
408 0x0, 0x1, 0x2, 0x3,
427 0x0, 0x1, 0x2, 0x3,
456 0x0, 0x1, 0x2, 0x3,
475 0x0, 0x1,
505 0x0, 0x1, 0x2, 0x3,
524 0x0, 0x1, 0x2, 0x3,
543 0x0, 0x1, 0x2, 0x3,
562 0x0, 0x1, 0x2, 0x3,
587 0x1 << w->shift, in mt_reg_set_clr_event()
588 0x1 << w->shift); in mt_reg_set_clr_event()
593 0x1 << w->shift, in mt_reg_set_clr_event()
594 0x1 << w->shift); in mt_reg_set_clr_event()
602 0x1 << w->shift, in mt_reg_set_clr_event()
603 0x1 << w->shift); in mt_reg_set_clr_event()
608 0x1 << w->shift, in mt_reg_set_clr_event()
609 0x1 << w->shift); in mt_reg_set_clr_event()
616 return 0; in mt_reg_set_clr_event()
628 0xffff, 0x1515); in mt_ncp_event()
631 0xfffe, 0x8C00); in mt_ncp_event()
640 return 0; in mt_ncp_event()
652 0xffef, 0x0008); in mt_sgen_event()
654 0xffff, 0x0101); in mt_sgen_event()
660 return 0; in mt_sgen_event()
670 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_in_event()
677 0xffff, 0x0006); in mt_aif_in_event()
680 0xffff, 0xC3A1); in mt_aif_in_event()
683 0xffff, 0x0003); in mt_aif_in_event()
686 0xffff, 0x000B); in mt_aif_in_event()
689 0xffff, 0x001E); in mt_aif_in_event()
693 0x330); in mt_aif_in_event()
696 0x300); in mt_aif_in_event()
699 0x8000, 0x8000); in mt_aif_in_event()
705 return 0; in mt_aif_in_event()
716 dev_dbg(priv->dev, "%s(), event 0x%x, hp_en_counter %d\n", in mt_hp_event()
724 else if (priv->hp_en_counter <= 0) in mt_hp_event()
725 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", in mt_hp_event()
733 0x0700, 0x0700); in mt_hp_event()
737 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f; in mt_hp_event()
738 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f; in mt_hp_event()
742 MT6351_ZCD_CON2, 0xffff, 0x0F9F); in mt_hp_event()
745 MT6351_ZCD_CON3, 0xffff, 0x001F); in mt_hp_event()
748 0x0001, 0x0001); in mt_hp_event()
751 0xffff, 0x2000); in mt_hp_event()
754 0xffff, 0x2100); in mt_hp_event()
757 0x0010, 0xE090); in mt_hp_event()
760 0xffff, 0x2140); in mt_hp_event()
769 0xffff, 0x2100); in mt_hp_event()
772 0xffff, 0x2000); in mt_hp_event()
775 0x0010, 0xF4EF); in mt_hp_event()
780 0x0700, 0x0300); in mt_hp_event()
792 if (priv->hp_en_counter > 0) in mt_hp_event()
794 else if (priv->hp_en_counter < 0) in mt_hp_event()
795 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", in mt_hp_event()
808 if (priv->hp_en_counter > 0) in mt_hp_event()
810 else if (priv->hp_en_counter < 0) in mt_hp_event()
811 dev_err(priv->dev, "%s(), hp_en_counter %d <= 0\n", in mt_hp_event()
818 0x0700, in mt_hp_event()
819 0x0000); in mt_hp_event()
823 0x0001, in mt_hp_event()
824 0x0000); in mt_hp_event()
833 return 0; in mt_hp_event()
843 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_out_event()
850 0xffff, 0x2062); in mt_aif_out_event()
853 0xffff, 0x2060); in mt_aif_out_event()
856 0xffff, 0x2061); in mt_aif_out_event()
860 0x000E, in mt_aif_out_event()
868 0x1 << 1, in mt_aif_out_event()
869 0x1 << 1); in mt_aif_out_event()
873 0x1 << 0, in mt_aif_out_event()
874 0x0 << 0); in mt_aif_out_event()
883 0x1 << 1, in mt_aif_out_event()
884 0x0 << 1); in mt_aif_out_event()
888 0x1 << 0, in mt_aif_out_event()
889 0x1 << 0); in mt_aif_out_event()
896 return 0; in mt_aif_out_event()
909 0x3 << 4, 0x0); in mt_adc_clkgen_event()
914 0x3 << 2, 0x0); in mt_adc_clkgen_event()
919 return 0; in mt_adc_clkgen_event()
932 0x3 << RG_AUDPREAMPLDCPRECHARGE, in mt_pga_left_event()
933 0x1 << RG_AUDPREAMPLDCPRECHARGE); in mt_pga_left_event()
936 0x3 << RG_AUDPREAMPLDCCEN, in mt_pga_left_event()
937 0x1 << RG_AUDPREAMPLDCCEN); in mt_pga_left_event()
943 0x3 << RG_AUDPREAMPLDCPRECHARGE, in mt_pga_left_event()
944 0x0 << RG_AUDPREAMPLDCPRECHARGE); in mt_pga_left_event()
949 return 0; in mt_pga_left_event()
962 0x3 << RG_AUDPREAMPRDCPRECHARGE, in mt_pga_right_event()
963 0x1 << RG_AUDPREAMPRDCPRECHARGE); in mt_pga_right_event()
966 0x3 << RG_AUDPREAMPRDCCEN, in mt_pga_right_event()
967 0x1 << RG_AUDPREAMPRDCCEN); in mt_pga_right_event()
973 0x3 << RG_AUDPREAMPRDCPRECHARGE, in mt_pga_right_event()
974 0x0 << RG_AUDPREAMPRDCPRECHARGE); in mt_pga_right_event()
979 return 0; in mt_pga_right_event()
990 /* MIC Bias 0 LowPower: 0_Normal */ in mt_mic_bias_0_event()
992 0x3 << RG_AUDMICBIAS0LOWPEN, 0x0); in mt_mic_bias_0_event()
995 0x7 << RG_AUDMICBIAS0VREF, in mt_mic_bias_0_event()
996 0x2 << RG_AUDMICBIAS0VREF); in mt_mic_bias_0_event()
1001 0x7 << RG_AUDMICBIAS0VREF, in mt_mic_bias_0_event()
1002 0x0 << RG_AUDMICBIAS0VREF); in mt_mic_bias_0_event()
1007 return 0; in mt_mic_bias_0_event()
1018 /* MIC Bias 1 LowPower: 0_Normal */ in mt_mic_bias_1_event()
1020 0x3 << RG_AUDMICBIAS1LOWPEN, 0x0); in mt_mic_bias_1_event()
1023 0x7 << RG_AUDMICBIAS1VREF, in mt_mic_bias_1_event()
1024 0x7 << RG_AUDMICBIAS1VREF); in mt_mic_bias_1_event()
1029 0x7 << RG_AUDMICBIAS1VREF, in mt_mic_bias_1_event()
1030 0x0 << RG_AUDMICBIAS1VREF); in mt_mic_bias_1_event()
1035 return 0; in mt_mic_bias_1_event()
1046 /* MIC Bias 2 LowPower: 0_Normal */ in mt_mic_bias_2_event()
1048 0x3 << RG_AUDMICBIAS2LOWPEN, 0x0); in mt_mic_bias_2_event()
1051 0x7 << RG_AUDMICBIAS2VREF, in mt_mic_bias_2_event()
1052 0x2 << RG_AUDMICBIAS2VREF); in mt_mic_bias_2_event()
1057 0x7 << RG_AUDMICBIAS2VREF, in mt_mic_bias_2_event()
1058 0x0 << RG_AUDMICBIAS2VREF); in mt_mic_bias_2_event()
1063 return 0; in mt_mic_bias_2_event()
1070 AUD_TOP_PDN_AFE_CTL_BIT, 1, NULL, 0),
1072 AUD_TOP_PDN_DAC_CTL_BIT, 1, NULL, 0),
1074 AUD_TOP_PDN_ADC_CTL_BIT, 1, NULL, 0),
1076 AUD_TOP_PWR_CLK_DIS_CTL_BIT, 1, NULL, 0),
1078 AUD_TOP_PDN_RESERVED_BIT, 1, NULL, 0),
1081 RG_NCP_ON_BIT, 0,
1086 0, 0, NULL, 0),
1090 RG_AUDGLB_PWRDN_VA32_BIT, 1, NULL, 0),
1092 RG_CLKSQ_EN_AUD_BIT, 0,
1112 SND_SOC_DAPM_SUPPLY("AFE_ON", MT6351_AFE_UL_DL_CON0, RG_AFE_ON_BIT, 0,
1113 NULL, 0),
1116 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
1118 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0,
1123 0, 0, NULL, 0),
1125 RG_NVREG_EN_VAUDP32_BIT, 0, NULL, 0),
1127 RG_RSTB_DECODER_VA32_BIT, 0, NULL, 0),
1129 RG_AUDIBIASPWRDN_VAUDP32_BIT, 1, NULL, 0),
1131 RG_LCLDO_DEC_EN_VA32_BIT, 0, NULL, 0),
1133 RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT, 0, NULL, 0),
1136 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1139 RG_AUDDACLPWRUP_VAUDP32_BIT, 0),
1141 RG_AUD_DAC_PWL_UP_VA32_BIT, 0, NULL, 0),
1144 RG_AUDDACRPWRUP_VAUDP32_BIT, 0),
1146 RG_AUD_DAC_PWR_UP_VA32_BIT, 0, NULL, 0),
1148 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
1151 RG_LOOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
1153 RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT, 0, NULL, 0),
1156 RG_AUDLOLPWRUP_VAUDP32_BIT, 0, NULL, 0),
1159 SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_in_mux_control),
1160 SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_in_mux_control),
1163 RG_AUDHPLPWRUP_VAUDP32_BIT, 0, NULL, 0,
1169 RG_AUDHPRPWRUP_VAUDP32_BIT, 0, NULL, 0,
1176 SND_SOC_DAPM_MUX("RCV Mux", SND_SOC_NOPM, 0, 0, &rcv_in_mux_control),
1179 RG_HSOUTPUTSTBENH_VAUDP32_BIT, 0, NULL, 0),
1181 RG_ABIDEC_RSVD0_VAUDP32_HS_BIT, 0, NULL, 0),
1184 RG_AUDHSPWRUP_VAUDP32_BIT, 0, NULL, 0),
1194 SGEN_C_DAC_EN_CTL_BIT, 0, NULL, 0),
1199 RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT, 0, NULL, 0),
1204 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
1206 UL_SRC_ON_TMP_CTL, 0,
1211 MT6351_LDO_VUSB33_CON0, RG_VUSB33_EN, 0,
1212 NULL, 0),
1215 NULL, 0),
1218 MT6351_LDO_VA18_CON0, RG_VA18_EN, 0, NULL, 0),
1221 NULL, 0),
1224 MT6351_AUDENC_ANA_CON3, RG_AUDADCCLKRSTB, 0,
1229 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
1232 SND_SOC_DAPM_MUX("ADC L Mux", SND_SOC_NOPM, 0, 0,
1234 SND_SOC_DAPM_MUX("ADC R Mux", SND_SOC_NOPM, 0, 0,
1238 MT6351_AUDENC_ANA_CON0, RG_AUDADCLPWRUP, 0),
1240 MT6351_AUDENC_ANA_CON1, RG_AUDADCRPWRUP, 0),
1242 SND_SOC_DAPM_MUX("PGA L Mux", SND_SOC_NOPM, 0, 0,
1244 SND_SOC_DAPM_MUX("PGA R Mux", SND_SOC_NOPM, 0, 0,
1247 SND_SOC_DAPM_PGA_E("PGA L", MT6351_AUDENC_ANA_CON0, RG_AUDPREAMPLON, 0,
1248 NULL, 0,
1251 SND_SOC_DAPM_PGA_E("PGA R", MT6351_AUDENC_ANA_CON1, RG_AUDPREAMPRON, 0,
1252 NULL, 0,
1257 SND_SOC_DAPM_SUPPLY_S("Mic Bias 0", SUPPLY_SUBSEQ_MICBIAS,
1258 MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS0, 0,
1263 MT6351_AUDENC_ANA_CON9, RG_AUDPWDBMICBIAS2, 0,
1268 MT6351_AUDENC_ANA_CON10, RG_AUDPWDBMICBIAS1, 0,
1273 RG_AUDMICBIAS1DCSW1NEN, 0,
1274 NULL, 0),
1330 {"AIN0", NULL, "Mic Bias 0"},
1411 regmap_update_bits(cmpnt->regmap, MT6351_TOP_CLKSQ, 0x0001, 0x0); in mt6351_codec_init_reg()
1414 0x1000, 0x1000); in mt6351_codec_init_reg()
1417 0x3800, 0x3800); in mt6351_codec_init_reg()
1420 0xe000, 0xe000); in mt6351_codec_init_reg()
1423 0x20, 0x20); in mt6351_codec_init_reg()
1426 0x8000, 0x8000); in mt6351_codec_init_reg()
1427 return 0; in mt6351_codec_init_reg()
1437 return 0; in mt6351_codec_probe()