20 #define CDC_D_REVISION1			(0xf000)
21 #define CDC_D_PERPH_SUBTYPE		(0xf005)
22 #define CDC_D_INT_EN_SET		(0xf015)
23 #define CDC_D_INT_EN_CLR		(0xf016)
28 #define CDC_D_CDC_RST_CTL		(0xf046)
30 #define RST_CTL_DIG_SW_RST_N_RESET	0
33 #define CDC_D_CDC_TOP_CLK_CTL		(0xf048)
38 #define CDC_D_CDC_ANA_CLK_CTL		(0xf049)
39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
40 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN	BIT(0)
46 #define CDC_D_CDC_DIG_CLK_CTL		(0xf04A)
47 #define DIG_CLK_CTL_RXD1_CLK_EN		BIT(0)
58 #define CDC_D_CDC_CONN_TX1_CTL		(0xf050)
59 #define CONN_TX1_SERIAL_TX1_MUX		GENMASK(1, 0)
60 #define CONN_TX1_SERIAL_TX1_ADC_1	0x0
61 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB	0x1
62 #define CONN_TX1_SERIAL_TX1_ZERO	0x2
64 #define CDC_D_CDC_CONN_TX2_CTL		(0xf051)
65 #define CONN_TX2_SERIAL_TX2_MUX		GENMASK(1, 0)
66 #define CONN_TX2_SERIAL_TX2_ADC_2	0x0
67 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB	0x1
68 #define CONN_TX2_SERIAL_TX2_ZERO	0x2
69 #define CDC_D_CDC_CONN_HPHR_DAC_CTL	(0xf052)
70 #define CDC_D_CDC_CONN_RX1_CTL		(0xf053)
71 #define CDC_D_CDC_CONN_RX2_CTL		(0xf054)
72 #define CDC_D_CDC_CONN_RX3_CTL		(0xf055)
73 #define CDC_D_CDC_CONN_RX_LB_CTL	(0xf056)
74 #define CDC_D_SEC_ACCESS		(0xf0D0)
75 #define CDC_D_PERPH_RESET_CTL3		(0xf0DA)
76 #define CDC_D_PERPH_RESET_CTL4		(0xf0DB)
77 #define CDC_A_REVISION1			(0xf100)
78 #define CDC_A_REVISION2			(0xf101)
79 #define CDC_A_REVISION3			(0xf102)
80 #define CDC_A_REVISION4			(0xf103)
81 #define CDC_A_PERPH_TYPE		(0xf104)
82 #define CDC_A_PERPH_SUBTYPE		(0xf105)
83 #define CDC_A_INT_RT_STS		(0xf110)
84 #define CDC_A_INT_SET_TYPE		(0xf111)
85 #define CDC_A_INT_POLARITY_HIGH		(0xf112)
86 #define CDC_A_INT_POLARITY_LOW		(0xf113)
87 #define CDC_A_INT_LATCHED_CLR		(0xf114)
88 #define CDC_A_INT_EN_SET		(0xf115)
89 #define CDC_A_INT_EN_CLR		(0xf116)
90 #define CDC_A_INT_LATCHED_STS		(0xf118)
91 #define CDC_A_INT_PENDING_STS		(0xf119)
92 #define CDC_A_INT_MID_SEL		(0xf11A)
93 #define CDC_A_INT_PRIORITY		(0xf11B)
94 #define CDC_A_MICB_1_EN			(0xf140)
98 #define MICB_1_EN_EXT_BYP_CAP		0
102 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA	(0x4)
104 #define MICB_1_EN_TX3_GND_SEL_MASK	BIT(0)
105 #define MICB_1_EN_TX3_GND_SEL_TX_GND	0
107 #define CDC_A_MICB_1_VAL		(0xf141)
112 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V	((0x16)  << 3)
113 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V	((0x4)  << 3)
114 #define CDC_A_MICB_1_CTL		(0xf142)
123 #define CDC_A_MICB_1_INT_RBIAS			(0xf143)
126 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE	0
130 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND	0
134 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE	0
137 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND	0
141 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE	0
142 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK	BIT(0)
143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
144 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND	0
146 #define CDC_A_MICB_2_EN			(0xf144)
150 #define CDC_A_TX_1_2_ATEST_CTL_2	(0xf145)
151 #define CDC_A_MASTER_BIAS_CTL		(0xf146)
152 #define CDC_A_MBHC_DET_CTL_1		(0xf147)
156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL	(0)
163 #define CDC_A_MBHC_DET_CTL_2		(0xf150)
169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK	BIT(0)
170 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN		BIT(0)
171 #define CDC_A_MBHC_FSM_CTL		(0xf151)
174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA	(0x3 << 4)
176 #define CDC_A_MBHC_DBNC_TIMER		(0xf152)
178 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS	(0x9 << 4)
179 #define CDC_A_MBHC_BTN0_ZDET_CTL_0	(0xf153)
180 #define CDC_A_MBHC_BTN1_ZDET_CTL_1	(0xf154)
181 #define CDC_A_MBHC_BTN2_ZDET_CTL_2	(0xf155)
182 #define CDC_A_MBHC_BTN3_CTL		(0xf156)
183 #define CDC_A_MBHC_BTN4_CTL		(0xf157)
190 #define CDC_A_MBHC_RESULT_1		(0xf158)
191 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK	GENMASK(4, 0)
192 #define CDC_A_TX_1_EN			(0xf160)
193 #define CDC_A_TX_2_EN			(0xf161)
194 #define CDC_A_TX_1_2_TEST_CTL_1		(0xf162)
195 #define CDC_A_TX_1_2_TEST_CTL_2		(0xf163)
196 #define CDC_A_TX_1_2_ATEST_CTL		(0xf164)
197 #define CDC_A_TX_1_2_OPAMP_BIAS		(0xf165)
198 #define CDC_A_TX_3_EN			(0xf167)
199 #define CDC_A_NCP_EN			(0xf180)
200 #define CDC_A_NCP_CLK			(0xf181)
201 #define CDC_A_NCP_FBCTRL		(0xf183)
204 #define CDC_A_NCP_BIAS			(0xf184)
205 #define CDC_A_NCP_VCTRL			(0xf185)
206 #define CDC_A_NCP_TEST			(0xf186)
207 #define CDC_A_NCP_CLIM_ADDR		(0xf187)
208 #define CDC_A_RX_CLOCK_DIVIDER		(0xf190)
209 #define CDC_A_RX_COM_OCP_CTL		(0xf191)
210 #define CDC_A_RX_COM_OCP_COUNT		(0xf192)
211 #define CDC_A_RX_COM_BIAS_DAC		(0xf193)
214 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK		BIT(0)
215 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE	BIT(0)
217 #define CDC_A_RX_HPH_BIAS_PA		(0xf194)
218 #define CDC_A_RX_HPH_BIAS_LDO_OCP	(0xf195)
219 #define CDC_A_RX_HPH_BIAS_CNP		(0xf196)
220 #define CDC_A_RX_HPH_CNP_EN		(0xf197)
221 #define CDC_A_RX_HPH_L_PA_DAC_CTL	(0xf19B)
224 #define CDC_A_RX_HPH_R_PA_DAC_CTL	(0xf19D)
228 #define CDC_A_RX_EAR_CTL			(0xf19E)
229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK		BIT(0)
230 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE	BIT(0)
236 #define CDC_A_SPKR_DAC_CTL		(0xf1B0)
238 #define SPKR_DAC_CTL_DAC_RESET_NORMAL	0
240 #define CDC_A_SPKR_DRV_CTL		(0xf1B2)
241 #define SPKR_DRV_CTL_DEF_MASK		0xEF
249 #define SPKR_DRV_GAIN_SET		BIT(0)
254 #define CDC_A_SPKR_OCP_CTL		(0xf1B4)
255 #define CDC_A_SPKR_PWRSTG_CTL		(0xf1B5)
256 #define SPKR_PWRSTG_CTL_DAC_EN_MASK	BIT(0)
257 #define SPKR_PWRSTG_CTL_DAC_EN		BIT(0)
258 #define SPKR_PWRSTG_CTL_MASK		0xE0
266 #define CDC_A_SPKR_DRV_DBG		(0xf1B7)
267 #define CDC_A_CURRENT_LIMIT		(0xf1C0)
268 #define CDC_A_BOOST_EN_CTL		(0xf1C3)
269 #define CDC_A_SLOPE_COMP_IP_ZERO	(0xf1C4)
270 #define CDC_A_SEC_ACCESS		(0xf1D0)
271 #define CDC_A_PERPH_RESET_CTL3		(0xf1DA)
272 #define CDC_A_PERPH_RESET_CTL4		(0xf1DB)
329 			CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
332 	SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
340 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
341 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
344 	SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
345 	SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
346 	SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
373 			    MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);  in pm8916_wcd_analog_micbias_enable()
388 	return 0;  in pm8916_wcd_analog_enable_micbias()
405 	return 0;  in pm8916_wcd_analog_enable_micbias_int()
446 				   0);  in pm8916_mbhc_configure_bias()
457 		vrefs = &priv->vref_btn_micb[0];  in pm8916_mbhc_configure_bias()
459 		vrefs = &priv->vref_btn_cs[0];  in pm8916_mbhc_configure_bias()
463 	for (i = 0; i <  MBHC_MAX_BUTTONS; i++) {  in pm8916_mbhc_configure_bias()
475 	return 0;  in pm8916_mbhc_configure_bias()
482 	u32 plug_type = 0;  in pm8916_wcd_setup_mbhc()
522 	snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);  in pm8916_wcd_setup_mbhc()
539 					      CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0);  in pm8916_wcd_analog_enable_micbias_int2()
599 		snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);  in pm8916_wcd_analog_enable_adc()
610 					    MICB_1_CTL_CFILT_REF_SEL_MASK, 0);  in pm8916_wcd_analog_enable_adc()
622 	return 0;  in pm8916_wcd_analog_enable_adc()
660 				    SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);  in pm8916_wcd_analog_enable_spk_pa()
666 				    RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);  in pm8916_wcd_analog_enable_spk_pa()
669 	return 0;  in pm8916_wcd_analog_enable_spk_pa()
690 				    RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0);  in pm8916_wcd_analog_enable_ear_pa()
694 				    RX_EAR_CTL_PA_SEL_MASK, 0);  in pm8916_wcd_analog_enable_ear_pa()
697 	return 0;  in pm8916_wcd_analog_enable_ear_pa()
701 	{CDC_A_RX_COM_OCP_CTL, 0xD1},
702 	{CDC_A_RX_COM_OCP_COUNT, 0xFF},
703 	{CDC_D_SEC_ACCESS, 0xA5},
704 	{CDC_D_PERPH_RESET_CTL3, 0x0F},
705 	{CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
706 	{CDC_A_NCP_FBCTRL, 0x28},
707 	{CDC_A_SPKR_DRV_CTL, 0x69},
708 	{CDC_A_SPKR_DRV_DBG, 0x01},
709 	{CDC_A_BOOST_EN_CTL, 0x5F},
710 	{CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
711 	{CDC_A_SEC_ACCESS, 0xA5},
712 	{CDC_A_PERPH_RESET_CTL3, 0x0F},
713 	{CDC_A_CURRENT_LIMIT, 0x82},
714 	{CDC_A_SPKR_DAC_CTL, 0x03},
715 	{CDC_A_SPKR_OCP_CTL, 0xE1},
716 	{CDC_A_MASTER_BIAS_CTL, 0x30},
725 	if (err != 0) {  in pm8916_wcd_analog_probe()
739 	snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);  in pm8916_wcd_analog_probe()
740 	snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);  in pm8916_wcd_analog_probe()
742 	for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)  in pm8916_wcd_analog_probe()
754 	return 0;  in pm8916_wcd_analog_probe()
762 			    RST_CTL_DIG_SW_RST_N_MASK, 0);  in pm8916_wcd_analog_remove()
864 	SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
865 	SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
866 	SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
867 	SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
877 	SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
880 			   0, 0, NULL, 0,
884 	SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
885 	SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
887 	SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
888 	SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
889 	SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
890 			   0),
891 	SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
892 	SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
893 	SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
894 			   0),
895 	SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
901 			   6, 0, NULL, 0,
905 	SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
906 	SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
908 	SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
909 	SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
912 	SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
915 	SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
919 	SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
920 	SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
922 	SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
925 	SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
929 	SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
933 	SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
937 	SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
941 	SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
946 	SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
947 	SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
949 	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
950 	SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
953 	SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
954 			    0),
955 	SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
956 			    0),
957 	SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
958 	SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
962 	SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
963 	SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
964 	SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
966 	SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
967 	SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
968 	SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
969 			    0),
972 	SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
974 	SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
985 	return 0;  in pm8916_wcd_analog_set_jack()
1001 		snd_soc_jack_report(priv->jack, 0, btn_mask);  in mbhc_btn_release_irq_handler()
1017 	case 0xf:  in mbhc_btn_press_irq_handler()
1020 	case 0x7:  in mbhc_btn_press_irq_handler()
1023 	case 0x3:  in mbhc_btn_press_irq_handler()
1026 	case 0x1:  in mbhc_btn_press_irq_handler()
1029 	case 0x0:  in mbhc_btn_press_irq_handler()
1085 		snd_soc_jack_report(priv->jack, 0, hs_jack_mask);  in pm8916_mbhc_switch_irq_handler()
1094 	[0] = {
1096 	       .id = 0,
1166 					  &priv->vref_btn_cs[0],  in pm8916_wcd_analog_parse_dt()
1168 	if (rval < 0) {  in pm8916_wcd_analog_parse_dt()
1173 						  &priv->vref_btn_micb[0],  in pm8916_wcd_analog_parse_dt()
1175 		if (rval < 0)  in pm8916_wcd_analog_parse_dt()
1184 	return 0;  in pm8916_wcd_analog_parse_dt()
1198 	if (ret < 0)  in pm8916_wcd_analog_spmi_probe()
1207 	for (i = 0; i < ARRAY_SIZE(supply_names); i++)  in pm8916_wcd_analog_spmi_probe()
1218 	if (ret < 0) {  in pm8916_wcd_analog_spmi_probe()
1224 	if (irq < 0) {  in pm8916_wcd_analog_spmi_probe()
1239 		if (irq < 0) {  in pm8916_wcd_analog_spmi_probe()
1253 		if (irq < 0) {  in pm8916_wcd_analog_spmi_probe()
1285 	return 0;  in pm8916_wcd_analog_spmi_remove()