Lines Matching +full:toggle +full:- +full:dither +full:- +full:input
1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
39 { 0x0D, 0x00 }, /* 0D Input Config */
40 { 0x0E, 0x1B }, /* 0E Line Input Level */
43 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
44 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
91 { 0x3E, 0x00 }, /* 3E Input Enable */
280 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
284 dev_err(max98090->component->dev, in max98090_reset()
301 -600, 600, 0);
304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
320 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
321 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
325 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
326 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
327 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
328 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
333 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
334 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
335 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
336 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
341 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
342 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
343 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
354 (struct soc_mixer_control *)kcontrol->private_value; in max98090_get_enab_tlv()
355 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_get_enab_tlv()
356 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_get_enab_tlv()
359 switch (mc->reg) { in max98090_get_enab_tlv()
361 select = &(max98090->pa1en); in max98090_get_enab_tlv()
364 select = &(max98090->pa2en); in max98090_get_enab_tlv()
367 select = &(max98090->sidetone); in max98090_get_enab_tlv()
370 return -EINVAL; in max98090_get_enab_tlv()
373 val = (val >> mc->shift) & mask; in max98090_get_enab_tlv()
377 val = val - 1; in max98090_get_enab_tlv()
384 ucontrol->value.integer.value[0] = val; in max98090_get_enab_tlv()
394 (struct soc_mixer_control *)kcontrol->private_value; in max98090_put_enab_tlv()
395 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_put_enab_tlv()
396 int sel_unchecked = ucontrol->value.integer.value[0]; in max98090_put_enab_tlv()
398 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_put_enab_tlv()
402 switch (mc->reg) { in max98090_put_enab_tlv()
404 select = &(max98090->pa1en); in max98090_put_enab_tlv()
407 select = &(max98090->pa2en); in max98090_put_enab_tlv()
410 select = &(max98090->sidetone); in max98090_put_enab_tlv()
413 return -EINVAL; in max98090_put_enab_tlv()
416 val = (val >> mc->shift) & mask; in max98090_put_enab_tlv()
418 if (sel_unchecked < 0 || sel_unchecked > mc->max) in max98090_put_enab_tlv()
419 return -EINVAL; in max98090_put_enab_tlv()
433 snd_soc_component_update_bits(component, mc->reg, in max98090_put_enab_tlv()
434 mask << mc->shift, in max98090_put_enab_tlv()
435 sel << mc->shift); in max98090_put_enab_tlv()
519 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
523 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
528 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
532 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
536 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
541 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
545 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
548 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
552 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
556 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
558 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
561 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
564 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
568 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
571 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
575 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
576 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
580 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
582 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
584 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
585 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
586 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
589 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
591 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
593 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
596 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
599 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
602 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
606 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
608 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
610 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
612 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
615 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
619 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
623 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
629 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
632 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
640 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
643 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
647 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
650 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
654 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
657 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
661 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
665 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
670 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
687 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
688 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
690 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
692 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
696 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
703 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
708 M98090_FLT_DMIC34HPF_NUM - 1, 0),
711 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
714 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
718 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
721 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
727 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
731 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
737 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_micinput_event()
740 unsigned int val = snd_soc_component_read(component, w->reg); in max98090_micinput_event()
742 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
748 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { in max98090_micinput_event()
749 max98090->pa1en = val - 1; /* Update for volatile */ in max98090_micinput_event()
751 max98090->pa2en = val - 1; /* Update for volatile */ in max98090_micinput_event()
758 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
759 val = max98090->pa1en + 1; in max98090_micinput_event()
761 val = max98090->pa2en + 1; in max98090_micinput_event()
768 return -EINVAL; in max98090_micinput_event()
771 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
772 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, in max98090_micinput_event()
775 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, in max98090_micinput_event()
784 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_shdn_event()
788 max98090->shdn_pending = true; in max98090_shdn_event()
1110 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1114 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1126 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1128 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1244 {"MIC1 Input", NULL, "MIC1"},
1245 {"MIC2 Input", NULL, "MIC2"},
1254 /* MIC1 input mux */
1258 /* MIC2 input mux */
1262 {"MIC1 Input", NULL, "MIC1 Mux"},
1263 {"MIC2 Input", NULL, "MIC2 Mux"},
1265 /* Left ADC input mixer */
1269 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1270 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1271 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1272 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1274 /* Right ADC input mixer */
1278 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1279 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1280 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1281 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1283 /* Line A input mixer */
1289 /* Line B input mixer */
1295 {"LINEA Input", NULL, "LINEA Mixer"},
1296 {"LINEB Input", NULL, "LINEB Mixer"},
1346 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1347 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1348 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1349 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1354 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1355 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1356 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1357 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1362 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1363 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1364 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1365 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1370 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1371 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1372 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1373 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1378 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1379 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1380 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1381 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1386 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1387 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1388 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1389 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1441 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1452 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1495 if (!max98090->sysclk) { in max98090_configure_bclk()
1496 dev_err(component->dev, "No SYSCLK configured\n"); in max98090_configure_bclk()
1500 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1501 dev_err(component->dev, "No audio clocks configured\n"); in max98090_configure_bclk()
1513 if ((pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1514 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1515 dev_dbg(component->dev, in max98090_configure_bclk()
1530 if ((user_pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1531 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1532 dev_dbg(component->dev, in max98090_configure_bclk()
1534 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", in max98090_configure_bclk()
1569 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1570 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1571 do_div(ni, (unsigned long long int)max98090->sysclk); in max98090_configure_bclk()
1572 dev_info(component->dev, "No better method found\n"); in max98090_configure_bclk()
1573 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); in max98090_configure_bclk()
1582 struct snd_soc_component *component = codec_dai->component; in max98090_dai_set_fmt()
1587 max98090->dai_fmt = fmt; in max98090_dai_set_fmt()
1588 cdata = &max98090->dai[0]; in max98090_dai_set_fmt()
1590 if (fmt != cdata->fmt) { in max98090_dai_set_fmt()
1591 cdata->fmt = fmt; in max98090_dai_set_fmt()
1596 /* Set to consumer mode PLL - MAS mode off */ in max98090_dai_set_fmt()
1603 max98090->master = false; in max98090_dai_set_fmt()
1607 if (max98090->tdm_slots == 4) { in max98090_dai_set_fmt()
1611 } else if (max98090->tdm_slots == 3) { in max98090_dai_set_fmt()
1620 max98090->master = true; in max98090_dai_set_fmt()
1623 dev_err(component->dev, "DAI clock mode unsupported"); in max98090_dai_set_fmt()
1624 return -EINVAL; in max98090_dai_set_fmt()
1641 dev_err(component->dev, "DAI format unsupported"); in max98090_dai_set_fmt()
1642 return -EINVAL; in max98090_dai_set_fmt()
1658 dev_err(component->dev, "DAI invert mode unsupported"); in max98090_dai_set_fmt()
1659 return -EINVAL; in max98090_dai_set_fmt()
1668 if (max98090->tdm_slots > 1) in max98090_dai_set_fmt()
1681 struct snd_soc_component *component = codec_dai->component; in max98090_set_tdm_slot()
1684 cdata = &max98090->dai[0]; in max98090_set_tdm_slot()
1687 return -EINVAL; in max98090_set_tdm_slot()
1689 max98090->tdm_slots = slots; in max98090_set_tdm_slot()
1690 max98090->tdm_width = slot_width; in max98090_set_tdm_slot()
1692 if (max98090->tdm_slots > 1) { in max98090_set_tdm_slot()
1708 cdata->fmt = 0; in max98090_set_tdm_slot()
1709 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); in max98090_set_tdm_slot()
1732 if (IS_ERR(max98090->mclk)) in max98090_set_bias_level()
1736 clk_disable_unprepare(max98090->mclk); in max98090_set_bias_level()
1738 ret = clk_prepare_enable(max98090->mclk); in max98090_set_bias_level()
1746 ret = regcache_sync(max98090->regmap); in max98090_set_bias_level()
1748 dev_err(component->dev, in max98090_set_bias_level()
1756 /* Set internal pull-up to lowest power mode */ in max98090_set_bias_level()
1759 regcache_mark_dirty(max98090->regmap); in max98090_set_bias_level()
1845 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); in max98090_find_divisor()
1867 m1 = pclk - dmic_table[i-1].pclk; in max98090_find_closest_pclk()
1868 m2 = dmic_table[i].pclk - pclk; in max98090_find_closest_pclk()
1870 return i - 1; in max98090_find_closest_pclk()
1876 return -EINVAL; in max98090_find_closest_pclk()
1894 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { in max98090_configure_dmic()
1902 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, in max98090_configure_dmic()
1906 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, in max98090_configure_dmic()
1917 struct snd_soc_component *component = dai->component; in max98090_dai_startup()
1919 unsigned int fmt = max98090->dai_fmt; in max98090_dai_startup()
1921 /* Remove 24-bit format support if it is not in right justified mode. */ in max98090_dai_startup()
1923 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; in max98090_dai_startup()
1924 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); in max98090_dai_startup()
1933 struct snd_soc_component *component = dai->component; in max98090_dai_hw_params()
1937 cdata = &max98090->dai[0]; in max98090_dai_hw_params()
1938 max98090->bclk = snd_soc_params_to_bclk(params); in max98090_dai_hw_params()
1940 max98090->bclk *= 2; in max98090_dai_hw_params()
1942 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1950 return -EINVAL; in max98090_dai_hw_params()
1953 if (max98090->master) in max98090_dai_hw_params()
1956 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
1959 if (max98090->lrclk < 24000) in max98090_dai_hw_params()
1967 if (max98090->lrclk < 50000) in max98090_dai_hw_params()
1974 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, in max98090_dai_hw_params()
1975 max98090->lrclk); in max98090_dai_hw_params()
1986 struct snd_soc_component *component = dai->component; in max98090_dai_set_sysclk()
1990 if (freq == max98090->sysclk) in max98090_dai_set_sysclk()
1993 if (!IS_ERR(max98090->mclk)) { in max98090_dai_set_sysclk()
1994 freq = clk_round_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
1995 clk_set_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2006 max98090->pclk = freq; in max98090_dai_set_sysclk()
2010 max98090->pclk = freq >> 1; in max98090_dai_set_sysclk()
2014 max98090->pclk = freq >> 2; in max98090_dai_set_sysclk()
2016 dev_err(component->dev, "Invalid master clock frequency\n"); in max98090_dai_set_sysclk()
2017 return -EINVAL; in max98090_dai_set_sysclk()
2020 max98090->sysclk = freq; in max98090_dai_set_sysclk()
2028 struct snd_soc_component *component = codec_dai->component; in max98090_dai_mute()
2041 struct snd_soc_component *component = dai->component; in max98090_dai_trigger()
2048 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2050 &max98090->pll_det_enable_work, in max98090_dai_trigger()
2056 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2057 schedule_work(&max98090->pll_det_disable_work); in max98090_dai_trigger()
2071 struct snd_soc_component *component = max98090->component; in max98090_pll_det_enable_work()
2080 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_pll_det_enable_work()
2086 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_pll_det_enable_work()
2090 &max98090->jack_work, in max98090_pll_det_enable_work()
2103 struct snd_soc_component *component = max98090->component; in max98090_pll_det_disable_work()
2105 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_pll_det_disable_work()
2114 struct snd_soc_component *component = max98090->component; in max98090_pll_work()
2121 dev_info_ratelimited(component->dev, "PLL unlocked\n"); in max98090_pll_work()
2130 /* Toggle shutdown OFF then ON */ in max98090_pll_work()
2153 struct snd_soc_component *component = max98090->component; in max98090_jack_work()
2158 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { in max98090_jack_work()
2177 dev_dbg(component->dev, "No Headset Detected\n"); in max98090_jack_work()
2179 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_jack_work()
2186 if (max98090->jack_state == in max98090_jack_work()
2189 dev_dbg(component->dev, in max98090_jack_work()
2206 dev_dbg(component->dev, "Headphone Detected\n"); in max98090_jack_work()
2208 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; in max98090_jack_work()
2215 dev_dbg(component->dev, "Headset Detected\n"); in max98090_jack_work()
2217 max98090->jack_state = M98090_JACK_STATE_HEADSET; in max98090_jack_work()
2224 dev_dbg(component->dev, "Unrecognized Jack Status\n"); in max98090_jack_work()
2228 snd_soc_jack_report(max98090->jack, status, in max98090_jack_work()
2235 struct snd_soc_component *component = max98090->component; in max98090_interrupt()
2244 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); in max98090_interrupt()
2246 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_interrupt()
2249 dev_err(component->dev, in max98090_interrupt()
2255 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); in max98090_interrupt()
2258 dev_err(component->dev, in max98090_interrupt()
2264 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", in max98090_interrupt()
2273 dev_err(component->dev, "M98090_CLD_MASK\n"); in max98090_interrupt()
2276 dev_dbg(component->dev, "M98090_SLD_MASK\n"); in max98090_interrupt()
2279 dev_dbg(component->dev, "M98090_ULK_MASK\n"); in max98090_interrupt()
2284 dev_dbg(component->dev, "M98090_JDET_MASK\n"); in max98090_interrupt()
2286 pm_wakeup_event(component->dev, 100); in max98090_interrupt()
2289 &max98090->jack_work, in max98090_interrupt()
2294 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); in max98090_interrupt()
2297 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); in max98090_interrupt()
2303 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2320 dev_dbg(component->dev, "max98090_mic_detect\n"); in max98090_mic_detect()
2322 max98090->jack = jack; in max98090_mic_detect()
2334 snd_soc_jack_report(max98090->jack, 0, in max98090_mic_detect()
2338 &max98090->jack_work, in max98090_mic_detect()
2389 dev_dbg(component->dev, "max98090_probe\n"); in max98090_probe()
2391 max98090->mclk = devm_clk_get(component->dev, "mclk"); in max98090_probe()
2392 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) in max98090_probe()
2393 return -EPROBE_DEFER; in max98090_probe()
2395 max98090->component = component; in max98090_probe()
2402 max98090->sysclk = (unsigned)-1; in max98090_probe()
2403 max98090->pclk = (unsigned)-1; in max98090_probe()
2404 max98090->master = false; in max98090_probe()
2406 cdata = &max98090->dai[0]; in max98090_probe()
2407 cdata->rate = (unsigned)-1; in max98090_probe()
2408 cdata->fmt = (unsigned)-1; in max98090_probe()
2410 max98090->lin_state = 0; in max98090_probe()
2411 max98090->pa1en = 0; in max98090_probe()
2412 max98090->pa2en = 0; in max98090_probe()
2416 dev_err(component->dev, "Failed to read device revision: %d\n", in max98090_probe()
2423 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); in max98090_probe()
2426 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); in max98090_probe()
2429 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); in max98090_probe()
2432 if (max98090->devtype != devtype) { in max98090_probe()
2433 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); in max98090_probe()
2434 max98090->devtype = devtype; in max98090_probe()
2437 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_probe()
2439 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); in max98090_probe()
2440 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, in max98090_probe()
2442 INIT_WORK(&max98090->pll_det_disable_work, in max98090_probe()
2471 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); in max98090_probe()
2474 dev_info(component->dev, "use default 2.8v micbias\n"); in max98090_probe()
2476 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); in max98090_probe()
2493 cancel_delayed_work_sync(&max98090->jack_work); in max98090_remove()
2494 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_remove()
2495 cancel_work_sync(&max98090->pll_det_disable_work); in max98090_remove()
2496 max98090->component = NULL; in max98090_remove()
2504 if (max98090->shdn_pending) { in max98090_seq_notifier()
2510 max98090->shdn_pending = false; in max98090_seq_notifier()
2552 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), in max98090_i2c_probe()
2555 return -ENOMEM; in max98090_i2c_probe()
2557 if (ACPI_HANDLE(&i2c->dev)) { in max98090_i2c_probe()
2558 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, in max98090_i2c_probe()
2559 &i2c->dev); in max98090_i2c_probe()
2561 dev_err(&i2c->dev, "No driver data\n"); in max98090_i2c_probe()
2562 return -EINVAL; in max98090_i2c_probe()
2564 driver_data = acpi_id->driver_data; in max98090_i2c_probe()
2568 driver_data = i2c_id->driver_data; in max98090_i2c_probe()
2571 max98090->devtype = driver_data; in max98090_i2c_probe()
2573 max98090->pdata = i2c->dev.platform_data; in max98090_i2c_probe()
2575 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", in max98090_i2c_probe()
2576 &max98090->dmic_freq); in max98090_i2c_probe()
2578 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; in max98090_i2c_probe()
2580 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); in max98090_i2c_probe()
2581 if (IS_ERR(max98090->regmap)) { in max98090_i2c_probe()
2582 ret = PTR_ERR(max98090->regmap); in max98090_i2c_probe()
2583 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in max98090_i2c_probe()
2587 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in max98090_i2c_probe()
2591 dev_err(&i2c->dev, "request_irq failed: %d\n", in max98090_i2c_probe()
2596 ret = devm_snd_soc_register_component(&i2c->dev, in max98090_i2c_probe()
2605 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); in max98090_i2c_shutdown()
2611 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2613 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2628 regcache_cache_only(max98090->regmap, false); in max98090_runtime_resume()
2632 regcache_sync(max98090->regmap); in max98090_runtime_resume()
2641 regcache_cache_only(max98090->regmap, true); in max98090_runtime_suspend()
2653 regcache_mark_dirty(max98090->regmap); in max98090_resume()
2658 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_resume()
2660 regcache_sync(max98090->regmap); in max98090_resume()