Lines Matching full:rx
653 "ZERO", "RX INT0_1 MIX1",
657 "ZERO", "RX INT1_1 MIX1",
661 "ZERO", "RX INT2_1 MIX1",
665 "ZERO", "RX INT0_2 MUX",
669 "ZERO", "RX INT1_2 MUX",
673 "ZERO", "RX INT2_2 MUX",
771 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
773 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
833 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
836 /* RX Macro */
1140 /* Update volatile list for rx/tx macros */ in rx_is_volatile_register()
1547 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_prim_interpolator_rate() local
1549 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1554 * to which interpolator input, the rx port in rx_macro_set_prim_interpolator_rate()
1592 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_mix_interpolator_rate() local
1594 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1638 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_hw_params() local
1649 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1662 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_channel_map() local
1670 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1691 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1854 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) in rx_macro_mclk_enable() argument
1856 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
1859 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
1873 rx->rx_mclk_users++; in rx_macro_mclk_enable()
1875 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
1876 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
1877 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
1880 rx->rx_mclk_users--; in rx_macro_mclk_enable()
1881 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
1898 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mclk_event() local
1903 rx_macro_mclk_enable(rx, true); in rx_macro_mclk_event()
1906 rx_macro_mclk_enable(rx, false); in rx_macro_mclk_event()
1985 struct rx_macro *rx, in rx_macro_config_compander() argument
2011 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2041 struct rx_macro *rx, in rx_macro_load_compander_coeff() argument
2052 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2066 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2082 struct rx_macro *rx, bool enable) in rx_macro_enable_softclip_clk() argument
2085 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2088 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2090 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2091 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2098 struct rx_macro *rx, int event) in rx_macro_config_softclip() argument
2101 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2106 rx_macro_enable_softclip_clk(component, rx, true); in rx_macro_config_softclip()
2115 rx_macro_enable_softclip_clk(component, rx, false); in rx_macro_config_softclip()
2122 struct rx_macro *rx, int event) in rx_macro_config_aux_hpf() argument
2126 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2140 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) in rx_macro_enable_clsh_block() argument
2142 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2143 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2145 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2146 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2150 struct rx_macro *rx, in rx_macro_config_classh() argument
2154 rx_macro_enable_clsh_block(rx, false); in rx_macro_config_classh()
2161 rx_macro_enable_clsh_block(rx, true); in rx_macro_config_classh()
2174 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2190 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2255 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_compander() local
2257 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2267 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_compander() local
2269 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2279 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_get() local
2282 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2295 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_put() local
2297 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2308 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2312 if (rx->active_ch_cnt[aif_rst]) { in rx_macro_mux_put()
2314 &rx->active_ch_mask[aif_rst]); in rx_macro_mux_put()
2315 rx->active_ch_cnt[aif_rst]--; in rx_macro_mux_put()
2323 &rx->active_ch_mask[rx_port_value]); in rx_macro_mux_put()
2324 rx->active_ch_cnt[rx_port_value]++; in rx_macro_mux_put()
2363 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_ear_mode() local
2365 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2373 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_ear_mode() local
2375 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2383 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_hd2_mode() local
2385 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2393 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_hd2_mode() local
2395 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2403 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_pwr_mode() local
2405 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2413 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_pwr_mode() local
2415 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2423 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_get() local
2425 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2434 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_put() local
2436 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2445 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_get() local
2447 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2456 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_put() local
2458 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2464 struct rx_macro *rx, in rx_macro_hphdelay_lutbypass() argument
2485 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2497 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2519 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_interp_clk() local
2528 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2536 rx_macro_load_compander_coeff(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2537 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2539 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2540 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2542 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2543 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2545 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2547 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2551 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2552 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2553 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2573 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2574 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2576 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2577 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2579 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2580 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2585 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2911 if (!(strcmp(w->name, "RX MIX TX0 MUX"))) in rx_macro_enable_echo()
2913 else if (!(strcmp(w->name, "RX MIX TX1 MUX"))) in rx_macro_enable_echo()
2918 if (!(strcmp(w->name, "RX MIX TX2 MUX"))) in rx_macro_enable_echo()
2938 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
2941 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
2944 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
2947 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
2950 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
2982 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
2986 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
2990 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
3006 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3008 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3011 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3015 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3019 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3024 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3025 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3026 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3027 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3028 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3029 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3030 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3031 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3032 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3034 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3038 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3042 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3047 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3049 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3051 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3054 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3055 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3056 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3057 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3058 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3059 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3061 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3064 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3067 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3071 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3072 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3073 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3089 {"RX AIF1 PB", NULL, "RX_MCLK"},
3090 {"RX AIF2 PB", NULL, "RX_MCLK"},
3091 {"RX AIF3 PB", NULL, "RX_MCLK"},
3092 {"RX AIF4 PB", NULL, "RX_MCLK"},
3094 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3095 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3096 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3097 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3098 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3099 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3101 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3102 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3103 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3104 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3105 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3106 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3108 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3109 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3110 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3111 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3112 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3113 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3115 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3116 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3117 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3118 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3119 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3120 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3129 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3130 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3131 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3132 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3133 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3134 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3135 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3136 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3137 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3138 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3139 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3140 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3141 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3142 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3143 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3144 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3145 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3146 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3147 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3148 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3149 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3150 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3151 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3152 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3153 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3154 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3155 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3156 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3157 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3158 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3160 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3161 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3162 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3163 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3164 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3165 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3166 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3167 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3168 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3169 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3170 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3171 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3172 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3173 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3174 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3175 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3176 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3177 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3178 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3179 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3180 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3181 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3182 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3183 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3184 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3185 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3186 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3187 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3188 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3189 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3191 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3192 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3193 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3194 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3195 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3196 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3197 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3198 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3199 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3200 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3201 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3202 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3203 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3204 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3205 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3206 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3207 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3208 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3209 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3210 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3211 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3212 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3213 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3214 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3215 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3216 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3217 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3218 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3219 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3220 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3222 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3223 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3224 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3225 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3226 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3227 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3228 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3229 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3230 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3232 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3233 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3234 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3235 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3236 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3237 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3238 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3239 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3240 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3241 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3242 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3243 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3244 {"RX AIF_ECHO", NULL, "RX_MCLK"},
3247 {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3248 {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3249 {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3250 {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3251 {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3252 {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3253 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3254 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3257 {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3258 {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3259 {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3260 {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3261 {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3262 {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3263 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3264 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3267 {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3268 {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3269 {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3270 {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3271 {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3272 {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3273 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3274 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3276 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3277 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3278 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3279 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3280 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3281 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3284 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3285 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3286 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3287 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3288 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3289 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3292 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3294 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3295 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3296 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3297 {"AUX_OUT", NULL, "RX INT2 MIX2"},
3394 {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3395 {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3396 {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3397 {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3398 {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3399 {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3404 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_component_probe() local
3406 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3427 rx->component = component; in rx_macro_component_probe()
3434 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_enable() local
3437 ret = clk_prepare_enable(rx->mclk); in swclk_gate_enable()
3439 dev_err(rx->dev, "unable to prepare mclk\n"); in swclk_gate_enable()
3443 rx_macro_mclk_enable(rx, true); in swclk_gate_enable()
3444 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3448 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3451 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3459 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_disable() local
3461 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3464 rx_macro_mclk_enable(rx, false); in swclk_gate_disable()
3465 clk_disable_unprepare(rx->mclk); in swclk_gate_disable()
3470 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_is_enabled() local
3473 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3493 static int rx_macro_register_mclk_output(struct rx_macro *rx) in rx_macro_register_mclk_output() argument
3495 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3497 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3502 parent_clk_name = __clk_get_name(rx->npl); in rx_macro_register_mclk_output()
3509 rx->hw.init = &init; in rx_macro_register_mclk_output()
3510 hw = &rx->hw; in rx_macro_register_mclk_output()
3511 ret = devm_clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3519 .name = "RX-MACRO",
3532 struct rx_macro *rx; in rx_macro_probe() local
3536 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); in rx_macro_probe()
3537 if (!rx) in rx_macro_probe()
3540 rx->macro = devm_clk_get_optional(dev, "macro"); in rx_macro_probe()
3541 if (IS_ERR(rx->macro)) in rx_macro_probe()
3542 return PTR_ERR(rx->macro); in rx_macro_probe()
3544 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); in rx_macro_probe()
3545 if (IS_ERR(rx->dcodec)) in rx_macro_probe()
3546 return PTR_ERR(rx->dcodec); in rx_macro_probe()
3548 rx->mclk = devm_clk_get(dev, "mclk"); in rx_macro_probe()
3549 if (IS_ERR(rx->mclk)) in rx_macro_probe()
3550 return PTR_ERR(rx->mclk); in rx_macro_probe()
3552 rx->npl = devm_clk_get(dev, "npl"); in rx_macro_probe()
3553 if (IS_ERR(rx->npl)) in rx_macro_probe()
3554 return PTR_ERR(rx->npl); in rx_macro_probe()
3556 rx->fsgen = devm_clk_get(dev, "fsgen"); in rx_macro_probe()
3557 if (IS_ERR(rx->fsgen)) in rx_macro_probe()
3558 return PTR_ERR(rx->fsgen); in rx_macro_probe()
3560 rx->pds = lpass_macro_pds_init(dev); in rx_macro_probe()
3561 if (IS_ERR(rx->pds)) in rx_macro_probe()
3562 return PTR_ERR(rx->pds); in rx_macro_probe()
3570 rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config); in rx_macro_probe()
3571 if (IS_ERR(rx->regmap)) { in rx_macro_probe()
3572 ret = PTR_ERR(rx->regmap); in rx_macro_probe()
3576 dev_set_drvdata(dev, rx); in rx_macro_probe()
3578 rx->dev = dev; in rx_macro_probe()
3581 clk_set_rate(rx->mclk, MCLK_FREQ); in rx_macro_probe()
3582 clk_set_rate(rx->npl, 2 * MCLK_FREQ); in rx_macro_probe()
3584 ret = clk_prepare_enable(rx->macro); in rx_macro_probe()
3588 ret = clk_prepare_enable(rx->dcodec); in rx_macro_probe()
3592 ret = clk_prepare_enable(rx->mclk); in rx_macro_probe()
3596 ret = clk_prepare_enable(rx->npl); in rx_macro_probe()
3600 ret = clk_prepare_enable(rx->fsgen); in rx_macro_probe()
3604 ret = rx_macro_register_mclk_output(rx); in rx_macro_probe()
3624 clk_disable_unprepare(rx->fsgen); in rx_macro_probe()
3626 clk_disable_unprepare(rx->npl); in rx_macro_probe()
3628 clk_disable_unprepare(rx->mclk); in rx_macro_probe()
3630 clk_disable_unprepare(rx->dcodec); in rx_macro_probe()
3632 clk_disable_unprepare(rx->macro); in rx_macro_probe()
3634 lpass_macro_pds_exit(rx->pds); in rx_macro_probe()
3641 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove() local
3643 clk_disable_unprepare(rx->mclk); in rx_macro_remove()
3644 clk_disable_unprepare(rx->npl); in rx_macro_remove()
3645 clk_disable_unprepare(rx->fsgen); in rx_macro_remove()
3646 clk_disable_unprepare(rx->macro); in rx_macro_remove()
3647 clk_disable_unprepare(rx->dcodec); in rx_macro_remove()
3649 lpass_macro_pds_exit(rx->pds); in rx_macro_remove()
3655 { .compatible = "qcom,sc7280-lpass-rx-macro" },
3656 { .compatible = "qcom,sm8250-lpass-rx-macro" },
3657 { .compatible = "qcom,sm8450-lpass-rx-macro" },
3658 { .compatible = "qcom,sc8280xp-lpass-rx-macro" },
3665 struct rx_macro *rx = dev_get_drvdata(dev); in rx_macro_runtime_suspend() local
3667 regcache_cache_only(rx->regmap, true); in rx_macro_runtime_suspend()
3668 regcache_mark_dirty(rx->regmap); in rx_macro_runtime_suspend()
3670 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_suspend()
3671 clk_disable_unprepare(rx->npl); in rx_macro_runtime_suspend()
3672 clk_disable_unprepare(rx->fsgen); in rx_macro_runtime_suspend()
3679 struct rx_macro *rx = dev_get_drvdata(dev); in rx_macro_runtime_resume() local
3682 ret = clk_prepare_enable(rx->mclk); in rx_macro_runtime_resume()
3688 ret = clk_prepare_enable(rx->npl); in rx_macro_runtime_resume()
3694 ret = clk_prepare_enable(rx->fsgen); in rx_macro_runtime_resume()
3699 regcache_cache_only(rx->regmap, false); in rx_macro_runtime_resume()
3700 regcache_sync(rx->regmap); in rx_macro_runtime_resume()
3704 clk_disable_unprepare(rx->npl); in rx_macro_runtime_resume()
3706 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_resume()
3728 MODULE_DESCRIPTION("RX macro driver");