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1 // SPDX-License-Identifier: GPL-2.0-only
3 * es8328.c -- ES8328 ALSA SoC Audio driver
5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
100 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
101 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
102 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
124 if (es8328->deemph) { in es8328_set_deemph()
127 if (abs(deemph_settings[i].rate - es8328->playback_fs) < in es8328_set_deemph()
128 abs(deemph_settings[best].rate - es8328->playback_fs)) in es8328_set_deemph()
137 dev_dbg(component->dev, "Set deemphasis %d\n", val); in es8328_set_deemph()
149 ucontrol->value.integer.value[0] = es8328->deemph; in es8328_get_deemph()
158 unsigned int deemph = ucontrol->value.integer.value[0]; in es8328_put_deemph()
162 return -EINVAL; in es8328_put_deemph()
164 if (es8328->deemph == deemph) in es8328_put_deemph()
171 es8328->deemph = deemph; in es8328_put_deemph()
189 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
191 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
193 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
195 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
235 /* Left Mixer */
238 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
239 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
240 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
243 /* Right Mixer */
245 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
246 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
248 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
254 /* Left PGA Mux */
262 /* Right PGA Mux */
278 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
279 "Mono (Right)", "Digital Mono"};
288 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
290 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
293 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
296 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
300 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
302 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
305 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
307 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
335 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
337 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
340 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
343 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
347 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
349 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
351 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
353 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
369 { "Left Line Mux", "Line 1", "LINPUT1" },
370 { "Left Line Mux", "Line 2", "LINPUT2" },
371 { "Left Line Mux", "PGA", "Left PGA Mux" },
372 { "Left Line Mux", "Differential", "Differential Mux" },
374 { "Right Line Mux", "Line 1", "RINPUT1" },
375 { "Right Line Mux", "Line 2", "RINPUT2" },
376 { "Right Line Mux", "PGA", "Right PGA Mux" },
377 { "Right Line Mux", "Differential", "Differential Mux" },
379 { "Left PGA Mux", "Line 1", "LINPUT1" },
380 { "Left PGA Mux", "Line 2", "LINPUT2" },
381 { "Left PGA Mux", "Differential", "Differential Mux" },
383 { "Right PGA Mux", "Line 1", "RINPUT1" },
384 { "Right PGA Mux", "Line 2", "RINPUT2" },
385 { "Right PGA Mux", "Differential", "Differential Mux" },
392 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
393 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
394 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
396 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
397 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
398 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
400 { "Left ADC", NULL, "Left ADC Mux" },
401 { "Right ADC", NULL, "Right ADC Mux" },
407 { "Left ADC", NULL, "ADC DIG" },
408 { "Right ADC", NULL, "ADC DIG" },
412 { "Left Line Mux", "Line 1", "LINPUT1" },
413 { "Left Line Mux", "Line 2", "LINPUT2" },
414 { "Left Line Mux", "PGA", "Left PGA Mux" },
415 { "Left Line Mux", "Differential", "Differential Mux" },
417 { "Right Line Mux", "Line 1", "RINPUT1" },
418 { "Right Line Mux", "Line 2", "RINPUT2" },
419 { "Right Line Mux", "PGA", "Right PGA Mux" },
420 { "Right Line Mux", "Differential", "Differential Mux" },
422 { "Left Out 1", NULL, "Left DAC" },
423 { "Right Out 1", NULL, "Right DAC" },
424 { "Left Out 2", NULL, "Left DAC" },
425 { "Right Out 2", NULL, "Right DAC" },
427 { "Left Mixer", "Playback Switch", "Left DAC" },
428 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
429 { "Left Mixer", "Right Playback Switch", "Right DAC" },
430 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
432 { "Right Mixer", "Left Playback Switch", "Left DAC" },
433 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
434 { "Right Mixer", "Playback Switch", "Right DAC" },
435 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
441 { "Left DAC", NULL, "DAC DIG" },
442 { "Right DAC", NULL, "DAC DIG" },
444 { "Left Out 1", NULL, "Left Mixer" },
445 { "LOUT1", NULL, "Left Out 1" },
446 { "Right Out 1", NULL, "Right Mixer" },
447 { "ROUT1", NULL, "Right Out 1" },
449 { "Left Out 2", NULL, "Left Mixer" },
450 { "LOUT2", NULL, "Left Out 2" },
451 { "Right Out 2", NULL, "Right Mixer" },
452 { "ROUT2", NULL, "Right Out 2" },
457 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, in es8328_mute()
465 struct snd_soc_component *component = dai->component; in es8328_startup()
468 if (es8328->provider && es8328->sysclk_constraints) in es8328_startup()
469 snd_pcm_hw_constraint_list(substream->runtime, 0, in es8328_startup()
471 es8328->sysclk_constraints); in es8328_startup()
480 struct snd_soc_component *component = dai->component; in es8328_hw_params()
487 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in es8328_hw_params()
492 if (es8328->provider) { in es8328_hw_params()
493 if (!es8328->sysclk_constraints) { in es8328_hw_params()
494 dev_err(component->dev, "No MCLK configured\n"); in es8328_hw_params()
495 return -EINVAL; in es8328_hw_params()
498 for (i = 0; i < es8328->sysclk_constraints->count; i++) in es8328_hw_params()
499 if (es8328->sysclk_constraints->list[i] == in es8328_hw_params()
503 if (i == es8328->sysclk_constraints->count) { in es8328_hw_params()
504 dev_err(component->dev, in es8328_hw_params()
507 return -EINVAL; in es8328_hw_params()
509 ratio = es8328->mclk_ratios[i]; in es8328_hw_params()
512 es8328->mclkdiv2 = 0; in es8328_hw_params()
517 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); in es8328_hw_params()
536 return -EINVAL; in es8328_hw_params()
539 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in es8328_hw_params()
544 es8328->playback_fs = params_rate(params); in es8328_hw_params()
557 struct snd_soc_component *component = codec_dai->component; in es8328_set_sysclk()
563 es8328->sysclk_constraints = NULL; in es8328_set_sysclk()
564 es8328->mclk_ratios = NULL; in es8328_set_sysclk()
570 es8328->sysclk_constraints = &constraints_11289; in es8328_set_sysclk()
571 es8328->mclk_ratios = ratios_11289; in es8328_set_sysclk()
577 es8328->sysclk_constraints = &constraints_12288; in es8328_set_sysclk()
578 es8328->mclk_ratios = ratios_12288; in es8328_set_sysclk()
581 return -EINVAL; in es8328_set_sysclk()
584 es8328->mclkdiv2 = mclkdiv2; in es8328_set_sysclk()
591 struct snd_soc_component *component = codec_dai->component; in es8328_set_dai_fmt()
602 es8328->provider = true; in es8328_set_dai_fmt()
608 es8328->provider = false; in es8328_set_dai_fmt()
611 return -EINVAL; in es8328_set_dai_fmt()
629 return -EINVAL; in es8328_set_dai_fmt()
634 return -EINVAL; in es8328_set_dai_fmt()
705 .name = "es8328-hifi-analog",
731 clk_disable_unprepare(es8328->clk); in es8328_suspend()
733 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_suspend()
734 es8328->supplies); in es8328_suspend()
736 dev_err(component->dev, "unable to disable regulators\n"); in es8328_suspend()
744 struct regmap *regmap = dev_get_regmap(component->dev, NULL); in es8328_resume()
750 ret = clk_prepare_enable(es8328->clk); in es8328_resume()
752 dev_err(component->dev, "unable to enable clock\n"); in es8328_resume()
756 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_resume()
757 es8328->supplies); in es8328_resume()
759 dev_err(component->dev, "unable to enable regulators\n"); in es8328_resume()
766 dev_err(component->dev, "unable to sync regcache\n"); in es8328_resume()
780 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
781 es8328->supplies); in es8328_component_probe()
783 dev_err(component->dev, "unable to enable regulators\n"); in es8328_component_probe()
788 es8328->clk = devm_clk_get(component->dev, NULL); in es8328_component_probe()
789 if (IS_ERR(es8328->clk)) { in es8328_component_probe()
790 dev_err(component->dev, "codec clock missing or invalid\n"); in es8328_component_probe()
791 ret = PTR_ERR(es8328->clk); in es8328_component_probe()
795 ret = clk_prepare_enable(es8328->clk); in es8328_component_probe()
797 dev_err(component->dev, "unable to prepare codec clk\n"); in es8328_component_probe()
804 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
805 es8328->supplies); in es8328_component_probe()
815 clk_disable_unprepare(es8328->clk); in es8328_remove()
817 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_remove()
818 es8328->supplies); in es8328_remove()
860 return -ENOMEM; in es8328_probe()
862 es8328->regmap = regmap; in es8328_probe()
864 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) in es8328_probe()
865 es8328->supplies[i].supply = supply_names[i]; in es8328_probe()
867 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), in es8328_probe()
868 es8328->supplies); in es8328_probe()